Jose Renau
Jose Renau
Processor of Computer Science Engineering, UCSC
Verified email at ucsc.edu - Homepage
TitleCited byYear
SESC simulator
J Renau
http://sesc. sourceforge. net, 2005
565*2005
POSH: a TLS compiler that exploits program structure
W Liu, J Tuck, L Ceze, W Ahn, K Strauss, J Renau, J Torrellas
Proceedings of the eleventh ACM SIGPLAN symposium on Principles and practice …, 2006
2812006
Cherry: Checkpointed early resource recycling in out-of-order microprocessors
JF Martínez, J Renau, MC Huang, M Prvulovic
35th Annual IEEE/ACM International Symposium on Microarchitecture, 2002 …, 2002
2732002
Positional adaptation of processors: application to energy reduction
MC Huang, J Renau, J Torrellas
30th Annual International Symposium on Computer Architecture, 2003 …, 2003
2332003
A framework for dynamic energy efficiency and temperature management
M Huang, J Renau, SM Yoo, J Torrellas
Proceedings 33rd Annual IEEE/ACM International Symposium on …, 2000
2052000
ESESC: A fast multicore simulator using time-based sampling
EK Ardestani, J Renau
2013 IEEE 19th International Symposium on High Performance Computer …, 2013
1172013
Tasking with out-of-order spawn in TLS chip multiprocessors: microarchitecture and compilation
J Renau, J Tuck, W Liu, L Ceze, K Strauss, J Torrellas
Proceedings of the 19th annual international conference on Supercomputing …, 2005
1062005
L1 data cache decomposition for energy efficiency
M Huang, J Renau, SM Yoo, J Torrellas
ISLPED'01: Proceedings of the 2001 International Symposium on Low Power …, 2001
972001
Characterizing processor thermal behavior
FJ Mesa-Martinez, EK Ardestani, J Renau
ACM SIGARCH Computer Architecture News 38 (1), 193-204, 2010
902010
Power model validation through thermal measurements
FJ Mesa-Martinez, J Nayfach-Battilana, J Renau
ACM SIGARCH Computer Architecture News 35 (2), 302-311, 2007
892007
Energy-efficient hybrid wakeup logic
M Huang, J Renau, J Torrellas
Proceedings of the international symposium on low power electronics and …, 2002
632002
Programming the FlexRAM parallel intelligent memory system
BB Fraguela, J Renau, P Feautrier, D Padua, J Torrellas
ACM Sigplan Notices 38 (10), 49-60, 2003
492003
CAVA: Using checkpoint-assisted value prediction to hide L2 misses
L Ceze, K Strauss, J Tuck, J Torrellas, J Renau
ACM Transactions on Architecture and Code Optimization (TACO) 3 (2), 182-208, 2006
462006
Thread-level speculation on a CMP can be energy efficient
J Renau, K Strauss, L Ceze, W Liu, S Sarangi, J Tuck, J Torrellas
Proceedings of the 19th annual international conference on Supercomputing …, 2005
412005
uComplexity: Estimating processor design effort
C Bazeghi, FJ Mesa-Martinez, J Renau
Proceedings of the 38th annual IEEE/ACM International Symposium on …, 2005
382005
Energy-efficient thread-level speculation
J Renau, K Strauss, L Ceze, W Liu, SR Sarangi, J Tuck, J Torrellas
IEEE Micro 26 (1), 80-91, 2006
372006
Measuring performance, power, and temperature from real processors
FJ Mesa-Martinez, M Brown, J Nayfach-Battilana, J Renau
Proceedings of the 2007 workshop on Experimental computer science, 16, 2007
342007
Effective optimistic-checker tandem core design through architectural pruning
F Mesa-Martinez, J Renau
Proceedings of the 40th Annual IEEE/ACM International Symposium on …, 2007
312007
Rerack: Power simulation for data centers with renewable energy generation
M Brown, J Renau
ACM SIGMETRICS Performance Evaluation Review 39 (3), 77-81, 2011
302011
CAVA: Hiding L2 misses with checkpoint-assisted value prediction
L Ceze, K Strauss, J Tuck, J Renau, J Torrellas
IEEE Computer Architecture Letters 3 (1), 7-7, 2004
292004
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