Erik Hagersten

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Citations	6339	1582
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David Black-SchafferProfessor, Uppsala UniversityVerified email at it.uu.se
Anders LandinCerebras systemsVerified email at landin.us
Mark D. HillProfessor of Computer Sciences and ECE, University of Wisconsin-MadisonVerified email at cs.wisc.edu
Andreas SembrantUppsala UniversityVerified email at it.uu.se
Seif HaridiProfessor of Computer Systems, KTH, RISEVerified email at ri.se
Nikos NikolerisPrincipal Research Engineer, Arm ResearchVerified email at arm.com
Stefanos KaxirasUppsala UniversityVerified email at it.uu.se
Trevor E. CarlsonNational University of SingaporeVerified email at comp.nus.edu.sg
Andreas SandbergPrincipal Research Engineer, Arm Ltd.Verified email at arm.com
David A. WoodUniversity of Wisconsin, MadisonVerified email at cs.wisc.edu
Per StenströmChalmers University of TechnologyVerified email at chalmers.se
Peter S MagnussonPresident, Magnusson InstituteVerified email at acm.org
Lieven EeckhoutProfessor of Computer Science and Engineering, Ghent UniversityVerified email at ugent.be
Alberto RosUniversity of MurciaVerified email at ditec.um.es
Stijn EyermanResearch Scientist, Intel BelgiumVerified email at intel.com
Margaret MartonosiProfessor of Computer Science, Princeton UniversityVerified email at princeton.edu
David J. LiljaProfessor of Electrical and Computer Engineering, University of MinnesotaVerified email at umn.edu
Felix WolfProfessor of Computer Science, TU DarmstadtVerified email at cs.tu-darmstadt.de
Germán CeballosUppsala UniversityVerified email at it.uu.se
Seznec AndreINRIA/IRISAVerified email at inria.fr

Erik Hagersten

Uppsala University

Verified email at it.uu.se - Homepage

Computer Architecture


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DDM-a cache-only memory architecture E Hagersten, A Landin, S Haridi Computer 25 (9), 44-54, 1992	405	1992
DDM-a cache-only memory architecture E Hagersten, A Landin, S Haridi Computer 25 (9), 44-54, 1992	401	1992
StatCache: A probabilistic approach to efficient and accurate data locality analysis E Berg, E Hagersten IEEE International Symposium on-ISPASS Performance Analysis of Systems and …, 2004	216	2004
Queue locks on cache coherent multiprocessors P Magnusson, A Landin, E Hagersten Proceedings of 8th International Parallel Processing Symposium, 165-171, 1994	205	1994
WildFire: A scalable path for SMPs E Hagersten, M Koster Proceedings Fifth International Symposium on High-Performance Computer …, 1999	160	1999
StatStack: Efficient modeling of LRU caches D Eklov, E Hagersten 2010 IEEE International Symposium on Performance Analysis of Systems …, 2010	149	2010
Multiprocessing system configured to perform efficient write operations EE Hagersten US Patent 5,749,095, 1998	147	1998
Fast data-locality profiling of native execution E Berg, E Hagersten Proceedings of the 2005 ACM SIGMETRICS international conference on …, 2005	128	2005
Multiprocessing computer system employing local and global address spaces and COMA and NUMA access modes EE Hagersten, PN Loewenstein US Patent 5,887,138, 1999	122	1999
Implementing snooping on a split-transaction computer system bus A Singhal, B Liencres, J Price, FM Cerauskis, D Broniarczyk, G Cheung, ... US Patent 5,978,874, 1999	104	1999
A statistical multiprocessor cache model E Berg, H Zeffer, E Hagersten 2006 IEEE International Symposium on Performance Analysis of Systems and …, 2006	88	2006
Race-free interconnection networks and multiprocessor consistency A Landin, E Hagersten, S Haridi Proceedings of the 18th Annual International Symposium on Computer …, 1991	84	1991
Hierarchical SMP computer system EE Hagersten, MD Hill US Patent 5,862,357, 1999	83	1999
Hierarchical backoff locks for nonuniform communication architectures Z Radovic, E Hagersten The Ninth International Symposium on High-Performance Computer Architecture …, 2003	82	2003
Efficient allocation of cache memory space in a computer system EE Hagersten, MD Hill US Patent 5,893,150, 1999	82	1999
Toward scalable cache only memory architectures E Hagersten Royal Institute of Technology, 1992	79	1992
Fast modeling of shared caches in multicore systems D Eklov, D Black-Schaffer, E Hagersten proceedings of the 6th international conference on high performance and …, 2011	76	2011
Gigaplane (TM): A High Performance Bus for Large SMPs A Singhal, D Broniarczyk, F Ceraukis, J Price, L Yuan, C Cheng, D Doblar, ... Hot Interconnects IV, 41-52, 1996	75	1996
Directory-based, shared-memory, scaleable multiprocessor computer system having deadlock-free transaction flow sans flow control protocol P Loewenstein, E Hagersten US Patent 6,141,692, 2000	74	2000
Cache pirating: Measuring the curse of the shared cache D Eklov, N Nikoleris, D Black-Schaffer, E Hagersten 2011 International Conference on Parallel Processing, 165-175, 2011	73	2011

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