| ASAP7: A 7-nm finFET predictive process design kit LT Clark, V Vashishtha, L Shifren, A Gujja, S Sinha, B Cline, ... Microelectronics Journal 53, 105-115, 2016 | 484 | 2016 |
| ASAP7 predictive design kit development and cell design technology co-optimization V Vashishtha, M Vangala, LT Clark 2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 992-998, 2017 | 52 | 2017 |
| Comparing bulk-Si FinFET and gate-all-around FETs for the 5 nm technology node V Vashishtha, LT Clark Microelectronics Journal 107, 104942, 2021 | 45 | 2021 |
| Design flows and collateral for the ASAP7 7nm FinFET predictive process design kit LT Clark, V Vashishtha, DM Harris, S Dietrich, Z Wang 2017 IEEE international conference on microelectronic systems education (MSE …, 2017 | 39 | 2017 |
| Robust 7-nm SRAM design on a predictive PDK V Vashishtha, M Vangala, P Sharma, LT Clark 2017 IEEE International Symposium on Circuits and Systems (ISCAS), 1-4, 2017 | 34 | 2017 |
| High performance low power pulse-clocked TMR circuits for soft-error hardness C Ramamurthy, S Chellappa, V Vashishtha, A Gogulamudi, LT Clark IEEE Transactions on Nuclear Science 62 (6), 3040-3048, 2015 | 19 | 2015 |
| Design technology co-optimization of back end of line design rules for a 7 nm predictive process design kit V Vashishtha, A Dosi, L Masand, LT Clark 2017 18th International Symposium on Quality Electronic Design (ISQED), 149-154, 2017 | 15 | 2017 |
| Advanced encryption system with dynamic pipeline reconfiguration for minimum energy operation S Chellappa, C Ramamurthy, V Vashishtha, LT Clark Sixteenth International Symposium on Quality Electronic Design, 201-206, 2015 | 14 | 2015 |
| Muller C-element self-corrected triple modular redundant logic with multithreading and low power modes C Ramamurthy, A Gujja, V Vashishtha, S Chellappa, LT Clark 2017 17th European Conference on Radiation and Its Effects on Components and …, 2017 | 9 | 2017 |
| A soft-error mitigated microprocessor with software controlled error reporting and recovery C Farnsworth, LT Clark, AR Gogulamudi, V Vashishtha, A Gujja IEEE Transactions on Nuclear Science 63 (4), 2241-2249, 2016 | 9 | 2016 |
| Muller C-element as majority gate for self-correcting triple modular redundant logic with low-overhead modes LT Clark, S Chellappa, V Vashishtha, A Gujja US Patent 9,780,788, 2017 | 7 | 2017 |
| Design with sub-10 nm FinFET technologies LT Clark, V Vashishtha 2017 IEEE Custom Integrated Circuits Conference (CICC), 1-87, 2017 | 5 | 2017 |
| ASAP5: A predictive PDK for the 5 nm node V Vashishtha, LT Clark Microelectronics Journal 126, 105481, 2022 | 4 | 2022 |
| Systematic analysis of the timing and power impact of pure lines and cuts routing for multiple patterning V Vashishtha, L Masand, A Dosi, C Ramamurthy, LT Clark Design-Process-Technology Co-optimization for Manufacturability XI 10148 …, 2017 | 4 | 2017 |
| A soft-error hardened process portable embedded microprocessor V Vashishtha, LT Clark, S Chellappa, AR Gogulamudi, A Gujja, ... 2015 IEEE Custom Integrated Circuits Conference (CICC), 1-4, 2015 | 4 | 2015 |
| Delay and power tradeoffs for static and dynamic register files V Vashishtha, A Gujja, LT Clark 2015 IEEE International Symposium on Circuits and Systems (ISCAS), 2900-2903, 2015 | 4 | 2015 |
| A FinFET-based framework for VLSI design at the 7 nm node V Vashishtha, LT Clark Energy Efficient Computing & Electronics, 3-49, 2019 | 2 | 2019 |
| ASAP7: A finFET-Based Framework for Academic VLSI Design at the 7 nm Node V Vashishtha, LT Clark Low Power Semiconductor Devices and Processes for Emerging Applications in …, 2018 | 2 | 2018 |
| Architectural and micro-architectural techniques for software controlled microprocessor soft-error mitigation AR Gogulamudi, LT Clark, C Farnsworth, S Chellappa, V Vashishtha 2015 15th European Conference on Radiation and Its Effects on Components and …, 2015 | 2 | 2015 |
| Power consumption improvement with residue code for fault tolerance on SRAM FPGA A Frédéric, E Thomas, V Vashishtha Proceedings of the 2011 Conference on Design & Architectures for Signal …, 2011 | 2 | 2011 |
