Ismet Bayraktaroglu
Ismet Bayraktaroglu
Oracle
Verified email at bayraktaroglu.org
TitleCited byYear
Test volume and application time reduction through scan chain concealment
I Bayraktaroglu, A Orailoglu
Proceedings of the 38th annual Design Automation Conference, 151-155, 2001
2442001
Test power reduction through minimization of scan chain transitions
O Sinanoglu, I Bayraktaroglu, A Orailoglu
Proceedings 20th IEEE VLSI Test Symposium (VTS 2002), 166-171, 2002
842002
Decompression hardware determination for test volume and time reduction through unified test pattern compaction and compression
I Bayraktaroglu, A Orailoglu
Proceedings. 21st VLSI Test Symposium, 2003., 113-118, 2003
732003
Test application time and volume compression through seed overlapping
W Rao, I Bayraktaroglu, A Orailoglu
Proceedings of the 40th annual Design Automation Conference, 732-737, 2003
632003
Concurrent application of compaction and compression for test time and data volume reduction in scan designs
I Bayraktaroglu, A Orailoglu
IEEE Transactions on Computers 52 (11), 1480-1489, 2003
602003
Microprocessor silicon debug based on failure propagation tracing
O Caty, P Dahlgren, I Bayraktaroglu
IEEE International Conference on Test, 2005., 10 pp.-293, 2005
592005
Cache resident functional microprocessor testing: Avoiding high speed io issues
I Bayraktaroglu, J Hunt, D Watkins
2006 IEEE International Test Conference, 1-7, 2006
492006
Scan power reduction through test data transition frequency analysis
O Sinanoglu, I Bayraktaroglu, A Orailoglu
Proceedings. International Test Conference, 844-850, 2002
492002
ANNSyS: an analog neural network synthesis system
I Bayraktaroğlu, AS Öğrenci, G Dündar, S Balkır, E Alpaydın
Neural Networks 12 (2), 325-338, 1999
331999
Deterministic partitioning techniques for fault diagnosis in scan-based BIST
I Bayraktaroglu, A Orailoglu
Proceedings International Test Conference 2000 (IEEE Cat. No. 00CH37159 …, 2000
312000
The construction of optimal deterministic partitionings in scan-based BIST fault diagnosis: mathematical foundations and cost-effective implementations
I Bayraktaroglu, A Orailoglu
IEEE Transactions on Computers 54 (1), 61-75, 2005
292005
Improved fault diagnosis in scan-based BIST via superposition
I Bayraktaroglu, A Orailoğlu
Proceedings of the 37th Annual Design Automation Conference, 55-58, 2000
292000
Enhancing reliability of RTL controller-datapath circuits via invariant-based concurrent test
Y Makris, I Bayraktaroglu, A Orailoglu
IEEE Transactions on Reliability 53 (2), 269-278, 2004
242004
Gate level fault diagnosis in scan-based BIST
I Bayraktaroglu, A Orailoglu
Proceedings of the conference on Design, automation and test in Europe, 376, 2002
242002
Reducing average and peak test power through scan chain modification
O Sinanoglu, I Bayraktaroglu, A Orailoglu
Journal of Electronic Testing 19 (4), 457-467, 2003
202003
Built-in self-test (BIST) of memory interconnect
O Caty, I Bayraktaroglu, A Majumdar
US Patent 7,096,393, 2006
172006
Concurrently programmable dynamic memory built-in self-test (BIST)
O Caty, I Bayraktaroglu
US Patent 7,062,694, 2006
152006
Diagnosis for scan-based BIST: Reaching deep into the signatures
I Bayraktaroglu, A Orailoglu
Proceedings Design, Automation and Test in Europe. Conference and Exhibition …, 2001
152001
Extracting sub-bands from signals in a frequency domain
VE Hanson, CG Ranson, T Kummetz
US Patent 10,326,630, 2019
142019
Cost-effective deterministic partitioning for rapid diagnosis in scan-based BIST
I Bayraktaroglu, A Orailoglu
IEEE design & test of computers 19 (1), 42-53, 2002
142002
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