| Device exploration of nanosheet transistors for sub-7-nm technology node D Jang, D Yakimets, G Eneman, P Schuddinck, MG Bardon, P Raghavan, ... IEEE Transactions on Electron Devices 64 (6), 2707-2713, 2017 | 254 | 2017 |
| Vertical GAAFETs for the ultimate CMOS scaling D Yakimets, G Eneman, P Schuddinck, TH Bao, MG Bardon, P Raghavan, ... IEEE Transactions on Electron Devices 62 (5), 1433-1439, 2015 | 209 | 2015 |
| Coarse-grained reconfigurable array architectures BD Sutter, P Raghavan, A Lambrechts Handbook of signal processing systems, 427-472, 2019 | 141 | 2019 |
| Understanding energy efficiency benefits of carbon nanotube field-effect transistors for digital VLSI G Hills, MG Bardon, G Doornbos, D Yakimets, P Schuddinck, R Baert, ... IEEE Transactions on Nanotechnology 17 (6), 1259-1269, 2018 | 133 | 2018 |
| Power aware FinFET and lateral nanosheet FET targeting for 3nm CMOS technology D Yakimets, MG Bardon, D Jang, P Schuddinck, Y Sherazi, P Weckx, ... 2017 IEEE International Electron Devices Meeting (IEDM), 20.4. 1-20.4. 4, 2017 | 111 | 2017 |
| Impact of Wire Geometry on Interconnect RC and Circuit Delay I Ciofi, A Contino, PJ Roussel, R Baert, VH Vega-Gonzalez, K Croes, ... IEEE Transactions on Electron Devices 63 (6), 2488-2496, 2016 | 104 | 2016 |
| Self-heating on bulk FinFET from 14nm down to 7nm node D Jang, E Bury, R Ritzenthaler, MG Bardon, T Chiarella, K Miyaguchi, ... 2015 IEEE International Electron Devices Meeting (IEDM), 11.6. 1-11.6. 4, 2015 | 99 | 2015 |
| Polarity control in WSe2 double-gate transistors GV Resta, S Sutar, Y Balaji, D Lin, P Raghavan, I Radu, F Catthoor, ... Scientific reports 6 (1), 29448, 2016 | 96 | 2016 |
| Future software-defined radio platforms and mapping flows M Palkovic, P Raghavan, M Li, A Dejonghe, L Van der Perre, F Catthoor IEEE Signal Processing Magazine 27 (2), 22-33, 2010 | 84 | 2010 |
| Comparison of reaction-diffusion and atomistic trap-based BTI models for logic gates H Kükner, S Khan, P Weckx, P Raghavan, S Hamdioui, B Kaczer, ... IEEE transactions on device and materials reliability 14 (1), 182-193, 2013 | 79 | 2013 |
| Extreme scaling enabled by 5 tracks cells: Holistic design-device co-optimization for FinFETs and lateral nanowires MG Bardon, Y Sherazi, P Schuddinck, D Jang, D Yakimets, P Debacker, ... 2016 IEEE International Electron Devices Meeting (IEDM), 28.2. 1-28.2. 4, 2016 | 78 | 2016 |
| Defect-based methodology for workload-dependent circuit lifetime projections-Application to SRAM P Weckx, B Kaczer, M Toledano-Luque, T Grasser, PJ Roussel, H Kukner, ... 2013 IEEE International Reliability Physics Symposium (IRPS), 3A. 4.1-3A. 4.7, 2013 | 70 | 2013 |
| Bias temperature instability analysis of FinFET based SRAM cells S Khan, I Agbo, S Hamdioui, H Kukner, B Kaczer, P Raghavan, F Catthoor 2014 Design, Automation & Test in Europe Conference & Exhibition (DATE), 1-6, 2014 | 65 | 2014 |
| Design and benchmarking of hybrid CMOS-spin wave device circuits compared to 10nm CMOS O Zografos, B Sorée, A Vaysset, S Cosemans, L Amaru, PE Gaillardon, ... 2015 IEEE 15th International Conference on Nanotechnology (IEEE-NANO), 686-689, 2015 | 62 | 2015 |
| Power breakdown analysis for a heterogeneous NoC platform running a video application A Lambrechts, P Raghavan, A Leroy, G Talavera, TV Aa, M Jayapala, ... 2005 IEEE International Conference on Application-Specific Systems …, 2005 | 61 | 2005 |
| BTI impact on logical gates in nano-scale CMOS technology S Khan, S Hamdioui, H Kukner, P Raghavan, F Catthoor 2012 IEEE 15th International Symposium on Design and Diagnostics of …, 2012 | 59 | 2012 |
| The impact of sequential-3D integration on semiconductor scaling roadmap A Mallik, A Vandooren, L Witters, A Walke, J Franco, Y Sherazi, P Weckx, ... 2017 IEEE International Electron Devices Meeting (IEDM), 32.1. 1-31.1. 4, 2017 | 58 | 2017 |
| A unified instruction set programmable architecture for multi-standard advanced forward error correction F Naessens, B Bougard, S Bressinck, L Hollevoet, P Raghavan, ... 2008 IEEE Workshop on Signal Processing Systems, 31-36, 2008 | 58 | 2008 |
| Vertical device architecture for 5nm and beyond: device & circuit implications AVY Thean, D Yakimets, TH Bao, P Schuddinck, S Sakhare, MG Bardon, ... 2015 Symposium on VLSI Technology (VLSI Technology), T26-T27, 2015 | 56 | 2015 |
| Implications of BTI-induced time-dependent statistics on yield estimation of digital circuits P Weckx, B Kaczer, M Toledano-Luque, P Raghavan, J Franco, ... IEEE Transactions on Electron Devices 61 (3), 666-673, 2014 | 55 | 2014 |
Liesbet Van der PerreKULeuvenVerified email at kuleuven.be
