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Gaurav Narang
Gaurav Narang
Phd Student at Washington State University
Verified email at iiitd.ac.in - Homepage
Title
Cited by
Cited by
Year
Statistical analysis of 64mb sram for optimizing yield and write performance
G Narang, P Sharma, M Jain, A Grover
2015 28th International Conference on VLSI Design, 411-416, 2015
52015
Floorplan and congestion aware framework for optimal SRAM selection for memory subsystems
G Narang, A Fell, PR Gupta, A Grover
2015 28th IEEE International System-on-Chip Conference (SOCC), 105-110, 2015
22015
Dynamic Power Management in Large Manycore Systems: A Learning-to-Search Framework
G Narang, A Deshwal, R Ayoub, M Kishinevsky, J Rao Doppa, PP Pande
ACM Transactions on Design Automation of Electronic Systems 28 (5), 1-21, 2023
12023
Heterogeneous memory assembly exploration using a floorplan and interconnect aware framework
PR Gupta, GS Visweswaran, G Narang, A Grover
2016 29th IEEE International System-on-Chip Conference (SOCC), 290-295, 2016
12016
Dataflow-Aware PIM-Enabled Manycore Architecture for Deep Learning Workloads
H Sharma, G Narang, JR Doppa, U Ogras, PP Pande
arXiv preprint arXiv:2403.19073, 2024
2024
Uncertainty-Aware Online Learning for Dynamic Power Management in Large Manycore Systems
G Narang, R Ayoub, M Kishinevsky, JR Doppa, PP Pande
2023 IEEE/ACM International Symposium on Low Power Electronics and Design …, 2023
2023
Floorplan aware framework for optimal SRAM selection for memory subsystems
G Narang, A Fell
2015
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