Zeye Liu
Zeye Liu
Verified email at andrew.cmu.edu
Title
Cited by
Cited by
Year
Regularizing activation distribution for training binarized deep networks
R Ding, TW Chin, Z Liu, D Marculescu
Proceedings of the IEEE/CVF Conference on Computer Vision and Pattern …, 2019
482019
Lightnn: Filling the gap between conventional deep neural networks and binarized networks
R Ding, Z Liu, R Shi, D Marculescu, RD Blanton
Proceedings of the on Great Lakes Symposium on VLSI 2017, 35-40, 2017
352017
Quantized deep neural networks for energy efficient hardware-based inference
R Ding, Z Liu, RDS Blanton, D Marculescu
2018 23rd Asia and South Pacific Design Automation Conference (ASP-DAC), 1-8, 2018
212018
Design reflection for optimal test-chip implementation
RDS Blanton, B Niewenhuis, ZD Liu
2015 IEEE International Test Conference (ITC), 1-10, 2015
202015
Achieving 100% cell-aware coverage by design
Z Liu, B Niewenhuis, S Mittal, RD Blanton
2016 Design, Automation & Test in Europe Conference & Exhibition (DATE), 109-114, 2016
142016
Flightnns: Lightweight quantized deep neural networks for fast and accurate inference
R Ding, Z Liu, TW Chin, D Marculescu, RD Blanton
Proceedings of the 56th Annual Design Automation Conference 2019, 1-6, 2019
92019
Test chip design for optimal cell-aware diagnosability
S Mittal, Z Liu, B Niewenhuis, RDS Blanton
2016 IEEE International Test Conference (ITC), 1-8, 2016
92016
Lightening the load with highly accurate storage-and energy-efficient lightnns
R Ding, Z Liu, RD Blanton, D Marculescu
ACM Transactions on Reconfigurable Technology and Systems (TRETS) 11 (3), 1-24, 2018
82018
Front-end layout reflection for test chip design
Z Liu, P Fynan, RD Blanton
2017 IEEE International Test Conference (ITC), 1-10, 2017
82017
Logic characterization vehicle design reflection via layout rewiring
P Fynan, Z Liu, B Niewenhuis, S Mittal, M Strajwas, RDS Blanton
2016 IEEE International Test Conference (ITC), 1-10, 2016
82016
Characterization of Locked Sequential Circuits via ATPG
D Duvalsaint, Z Liu, A Ravikumar, RD Blanton
2019 IEEE International Test Conference in Asia (ITC-Asia), 97-102, 2019
72019
CompactNet: High accuracy deep neural network optimized for on-chip implementation
A Goel, Z Liu, RD Blanton
2018 IEEE International Conference on Big Data (Big Data), 4723-4729, 2018
42018
Back-end Layout Reflection for Test Chip Design
Z Liu, RD Blanton
2018 IEEE 36th International Conference on Computer Design (ICCD), 456-463, 2018
32018
Improving Test Chip Design Efficiency via Machine Learning
Z Liu, Q Huang, C Fang, RD Blanton
2019 IEEE International Test Conference (ITC), 1-10, 2019
22019
A unified solution to reduce test power and test volume for Test-per-scan schemes
S Lei, Z Wang, Z Liu, F Liang
IEICE Electronics Express 7 (18), 1364-1369, 2010
22010
IPSA: Integer Programming via Sparse Approximation for Efficient Test-Chip Design
Q Huang, C Fang, Z Liu, R Ding, RDS Blanton
2019 IEEE 37th International Conference on Computer Design (ICCD), 11-19, 2019
12019
Logic characterization vehicle design for yield learning
B Niewenhuis, ZD Liu, S Mittal, RDS Blanton
2016 27th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC …, 2016
12016
A Low Power Test Pattern Generator for BIST
S Lei, F Liang, Z Liu, X Wang, Z Wang
IEICE transactions on electronics 93 (5), 696-702, 2010
12010
Flexible, lightweight quantized deep neural networks
R Ding, Z Liu, TW Chin, D Marculescu, RD Blanton
US Patent App. 16/887,988, 2020
2020
High Defect-Density Yield Learning using Three-Dimensional Logic Test Chips
Z Liu, RDS Blanton
2020 IEEE International Test Conference (ITC), 1-10, 2020
2020
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