| Design of low power TPG using LP-LFSR A Kavitha, G Seetharaman, TN Prabakar, S Shrinithi 2012 Third International Conference on Intelligent Systems Modelling and …, 2012 | 35 | 2012 |
| Multi bit random and burst error correction code with crosstalk avoidance for reliable on chip interconnection links M Maheswari, G Seetharaman Microprocessors and Microsystems 37 (4-5), 420-429, 2013 | 22 | 2013 |
| Design and FPGA implementation of self tuned wavepipelined filters G Seetharaman, B Venkataramani, G Lakshminarayanan IETE journal of research 52 (4), 281-286, 2006 | 18 | 2006 |
| Enhanced low complex double error correction coding with crosstalk avoidance for reliable on-chip interconnection link M Maheswari, G Seetharaman Journal of Electronic Testing 30, 387-400, 2014 | 13 | 2014 |
| Design of a novel error correction coding with crosstalk avoidance for reliable on-chip interconnection link M Maheswari, G Seetharaman International journal of computer applications in technology 49 (1), 80-88, 2014 | 10 | 2014 |
| A novel architecture for an efficient implementation of image compression using 2D-DWT N Parvatham, S Gopalakrishnan 2012 Third International Conference on Intelligent Systems Modelling and …, 2012 | 8 | 2012 |
| A functionality-based runtime relocation system for circuits on heterogeneous FPGAs G Enemali, A Adetomi, G Seetharaman, T Arslan IEEE Transactions on Circuits and Systems II: Express Briefs 65 (5), 612-616, 2018 | 7 | 2018 |
| Hamming product code based multiple bit error correction coding scheme using keyboard scan based decoding for on chip interconnects links M Maheswari, G Seetharaman Applied Mechanics and Materials 241, 2457-2461, 2013 | 7 | 2013 |
| Implementation of application specific network on chip architectures on reconfigurable devices using topology generation algorithm with genetic algorithm based optimization … M Maheswari, G Seetharaman ICIP, 436-445, 2012 | 7 | 2012 |
| Reliable fault-tolerance routing technique for network-on-chip interconnect Jayshree, G Seetharaman, D Pati Intelligent Sustainable Systems: Proceedings of ICISS 2021, 767-775, 2022 | 6 | 2022 |
| Automation schemes for FPGA implementation of wave-pipelined circuits G Seetharaman, B Venkataramani ACM Transactions on Reconfigurable Technology and Systems (TRETS) 2 (2), 1-19, 2009 | 6 | 2009 |
| SOC implementation of wave-pipelined circuits G Seetharaman, B Venkataramani 2007 International Conference on Field-Programmable Technology, 9-16, 2007 | 6 | 2007 |
| Design and area performance energy consumption comparison of secured network-on-chip with PTP and bus interconnections Jayshree, G Seetharaman, D Pati Journal of The Institution of Engineers (India): Series B 103 (5), 1479-1491, 2022 | 5 | 2022 |
| Custom NoC topology generation using discrete antlion trapping mechanism P Narayanasamy, S Gopalakrishnan, S Muthurathinam Integration 76, 76-86, 2021 | 5 | 2021 |
| A modified algorithm for removal of salt and pepper noise in color images V Adhinarayanan, SP Sheebha, L Sriraman, TN Prabakar, ... 2012 Third International Conference on Intelligent Systems Modelling and …, 2012 | 5 | 2012 |
| Automation techniques for implementation of hybrid wave-pipelined 2D DWT G Seetharaman, B Venkataramani, G Lakshminarayanan Journal of Real-Time Image Processing 3, 217-229, 2008 | 5 | 2008 |
| Design and FPGA implementation of self-tuned wave-pipelined filters with distributed arithmetic algorithm G Seetharaman, B Venkataramani, G Lakshminarayanan Circuits, Systems & Signal Processing 27, 261-276, 2008 | 5 | 2008 |
| Energy consumption and performance comparison of DE optimization and PSO-based IP-core mapping technique for 2D and 3D network-on-chip G Seetharaman, D Pati Semiconductor Science and Technology 36 (8), 085015, 2021 | 4 | 2021 |
| Design and analysis of novel interconnects with network-on-chip LVDS transmitter for low delay G Seetharaman 2018 NASA/ESA Conference on Adaptive Hardware and Systems (AHS), 204-209, 2018 | 4 | 2018 |
| VLSI implementation of hybrid wave-pipelined 2D DWT using lifting scheme G Seetharaman, B Venkataramani, G Lakshminarayanan VLSI Design 2008, 2008 | 4 | 2008 |
adhinarayanan venkatasubramaniangitam university bangloreVerified email at gitam.edu
adhinarayanan venkatasubramaniangitam university bangloreVerified email at gitam.edu