engin afacan
TitleCited byYear
Adaptive sized quasi-monte carlo based yield aware analog circuit optimization tool
E Afacan, G Berkol, AE Pusane, G Dündar, F Başkaya
2014 5th European Workshop on CMOS Variability (VARI), 1-6, 2014
172014
A two-step layout-in-the-loop design automation tool
G Berkol, A Unutulmaz, E Afacan, G Dündar, FV Fernandez, AE Pusane, ...
2015 IEEE 13th International New Circuits and Systems Conference (NEWCAS), 1-4, 2015
132015
An FPGA-based multiple-output PWM pulse generator for ultrasonic cleaning machines
A Tangel, M Yakut, E Afacan, U Güvenç, H Şengül
2010 international conference on applied electronics, 1-4, 2010
122010
A deterministic aging simulator and an analog circuit sizing tool robust to aging phenomena
E Afacan, G Berkol, G Dündar, AE Pusane, F Başkaya
2015 International Conference on Synthesis, Modeling, Analysis and …, 2015
92015
A novel yield aware multi-objective analog circuit optimization tool
G Berkol, E Afacan, G Dündar, AE Pusane, F Başkaya
2015 IEEE International Symposium on Circuits and Systems (ISCAS), 2652-2655, 2015
92015
Sensitivity based methodologies for process variation aware analog ic optimization
E Afacan, G Berkol, F Başkaya, G Dündar
2014 10th Conference on Ph. D. Research in Microelectronics and Electronics …, 2014
92014
Reliability assessment of CMOS differential cross-coupled LC oscillators and a novel on chip self-healing approach against aging phenomena
E Afacan, G Dundar, F Baskaya
Microelectronics Reliability 54 (2), 397-403, 2014
92014
A lifetime-aware analog circuit sizing tool
E Afacan, G Berkol, G Dundar, AE Pusane, F Baskaya
Integration 55, 349-356, 2016
82016
A mixed domain sizing approach for RF circuit synthesis
E Afacan, G Dündar
2016 IEEE 19th International Symposium on Design and Diagnostics of …, 2016
82016
A hybrid quasi monte carlo method for yield aware analog circuit sizing tool
E Afacan, G Berkol, AE Pusane, G Dündar, F Başkaya
2015 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2015
72015
Analog design methodologies for reliability in nanoscale CMOS circuits
E Afacan, MB Yelten, G Dündar
2017 14th International Conference on Synthesis, Modeling, Analysis and …, 2017
52017
Model based hierarchical optimization strategies for analog design automation
E Afacan, S Ay, FV Fernandez, G Dündar, F Bas
2014 Design, Automation & Test in Europe Conference & Exhibition (DATE), 1-4, 2014
52014
Reliability enhancement using in-field monitoring and recovery for RF circuits
D Chang, S Ozev, B Bakkaloglu, S Kiaei, E Afacan, G Dundar
2014 IEEE 32nd VLSI Test Symposium (VTS), 1-6, 2014
42014
An Analog/RF Circuit Synthesis and Design Assistant Tool for Analog IP: DATA-IP
E Kaya, E Afacan, G Dundar
2018 15th International Conference on Synthesis, Modeling, Analysis and …, 2018
32018
Semi-empirical aging model development via accelerated aging test
E Afacan, G Dündar, AE Pusane, F Başkaya
2016 13th International Conference on Synthesis, Modeling, Analysis and …, 2016
32016
Inversion coefficient optimization based Analog/RF circuit design automation
E Afacan
Microelectronics Journal 83, 86-93, 2019
22019
Inversion coefficient optimization assisted analog circuit sizing tool
E Afacan, G Dündar
2017 14th International Conference on Synthesis, Modeling, Analysis and …, 2017
22017
An analog circuit synthesis tool based on efficient and reliable yield estimation
E Afacan, G Berkol, G Dundar, AE Pusane, F Baskaya
Microelectronics Journal 54, 14-22, 2016
22016
Efficient signature selection tool for sense & react systems
E Afacan, G Dündar, AE Pusane, F Başkaya, MB Yelten
2016 13th International Conference on Synthesis, Modeling, Analysis and …, 2016
22016
A comprehensive analysis on differential cross-coupled CMOS LC oscillators via multi-objective optimization
E Afacan, G Dundar
Integration, 2019
12019
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Articles 1–20