Sergey Gribok
Sergey Gribok
Intel PSG
Verified email at intel.com
Title
Cited by
Cited by
Year
Digitally Controlled Delay Line for a Structured ASIC Having a Via Configurable Fabric for High-Speed Interface
A Andreev, S Gribok, M Serban, M Verita, KW Sim, KH Lew
US Patent App. 13/649,584, 2014
202014
Clock network fishbone architecture for a structured ASIC manufactured on a 28 NM CMOS process lithographic node
A Andreev, A Nikishin, S Gribok, PC Tan, C Choo
US Patent 8,629,548, 2014
192014
Low complexity LDPC encoding algorithm
S Gribok, A Andreev, I Vikhliantsev
US Patent 7,913,149, 2011
172011
Why compete when you can work together: Fpga-asic integration for persistent rnns
E Nurvitadhi, D Kwon, A Jafari, A Boutros, J Sim, P Tomson, H Sumbul, ...
2019 IEEE 27th Annual International Symposium on Field-Programmable Customá…, 2019
162019
Parallel LDPC decoder
A Andreev, I Vikhliantsev, S Gribok
US Patent 7,934,139, 2011
132011
Via-configurable high-performance logic block involving transistor chains
A Andreev, S Gribok, RL Scepanovic, P Tan, C Kung
US Patent 8,957,398, 2015
102015
MEMS-based switching
H Schmit, S Gribok
US Patent 8,436,700, 2013
102013
Systems and methods for pipelined analog to digital conversion
S Gribok, C Ito, W Loh, E Chmelar
US Patent 7,656,340, 2010
102010
RRAM memory error emulation
AE Andreev, V Vukovic, S Gribok
US Patent 7,493,519, 2009
72009
Memory BISR architecture for a slice
AE Andreev, SV Gribok, AA Bolotov
US Patent 7,430,694, 2008
72008
Extracting int8 multipliers from int18 multipliers
M Langhammer, B Pasca, G Baeckler, S Gribok
2019 29th International Conference on Field Programmable Logic andá…, 2019
62019
Fractal synthesis: Invited tutorial
M Langhammer, G Baeckler, S Gribok
Proceedings of the 2019 ACM/SIGDA International Symposium on Fieldá…, 2019
62019
Об одной модели рекурсивных схем из функциональных элементов
СВ Грибок
Вестн. Моск. ун-та. Сер. 15. Вычисл. матем. и киберн, 31, 2002
5*2002
Об одном базисе для схем из клеточных элементов
СВ Грибок
Вестник Московского Университета, сер 15, 36-39, 1999
51999
Via-configurable high-performance logic block architecture
A Andreev, S Gribok, R Scepanovic
US Patent 8,735,857, 2014
42014
Methods and apparatus for programmable decoding of a plurality of code types
A Andreev, S Gribok, O Izyumin, R Scepanovic, I Vikhliantsev, V Vukovic
US Patent 8,035,537, 2011
42011
Evaluating and Enhancing Intel« Stratix« 10 FPGAs for Persistent Real-Time AI
E Nurvitadhi, D Kwon, A Jafari, A Boutros, J Sim, P Tomson, H Sumbul, ...
Proceedings of the 2019 ACM/SIGDA International Symposium on Fieldá…, 2019
32019
Variable node processing unit
A Andreev, S Gribok, O Izyumin
US Patent 8,443,033, 2013
32013
Cryptographic random number generator using finite field operations
S Gribok, A Andreev, S Gashkov
US Patent 8,250,129, 2012
32012
Built in self test transport controller architecture
S Gribok, A Andreev, I Pavisic
US Patent 7,546,505, 2009
32009
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Articles 1–20