| Nvmain 2.0: A user-friendly memory simulator to model (non-) volatile memory systems M Poremba, T Zhang, Y Xie IEEE Computer Architecture Letters 14 (2), 140-143, 2015 | 275 | 2015 |
| Modular routing design for chiplet-based systems J Yin, Z Lin, O Kayiran, M Poremba, MSB Altaf, NE Jerger, GH Loh 2018 ACM/IEEE 45th Annual International Symposium on Computer Architecture …, 2018 | 132 | 2018 |
| Design and Analysis of an APU for Exascale Computing T Vijayaraghavan, Y Eckert, GH Loh, MJ Schulte, M Ignatowski, ... 2017 IEEE International Symposium on High Performance Computer Architecture …, 2017 | 104 | 2017 |
| Lost in abstraction: Pitfalls of analyzing GPUs at the intermediate language level A Gutierrez, BM Beckmann, A Dutu, J Gross, M LeBeane, J Kalamatianos, ... 2018 IEEE International Symposium on High Performance Computer Architecture …, 2018 | 99 | 2018 |
| TS-router: On maximizing the quality-of-allocation in the on-chip network YY Chang, YSC Huang, M Poremba, V Narayanan, Y Xie, CT King 2013 IEEE 19th International Symposium on High Performance Computer …, 2013 | 43 | 2013 |
| Evaluation of using inductive/capacitive-coupling vertical interconnects in 3D network-on-chip J Ouyang, J Xie, M Poremba, Y Xie 2010 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 477-482, 2010 | 43 | 2010 |
| There and back again: Optimizing the interconnect in networks of memory cubes M Poremba, I Akgun, J Yin, O Kayiran, Y Xie, GH Loh ACM SIGARCH Computer Architecture News 45 (2), 678-690, 2017 | 30 | 2017 |
| Exploring design space of 3d nvm and edram caches using destiny tool S Mittal, M Poremba, J Vetter, Y Xie Oak Ridge National Laboratory, USA, Tech. Rep. ORNL/TM-2014/636, 2014 | 22 | 2014 |
| Efficient synthetic traffic models for large, complex SoCs J Yin, O Kayiran, M Poremba, NE Jerger, GH Loh 2016 IEEE International Symposium on High Performance Computer Architecture …, 2016 | 17 | 2016 |
| Heterogeneous architecture design with emerging 3D and non-volatile memory technologies Q Zou, M Poremba, R He, W Yang, J Zhao, Y Xie The 20th Asia and South Pacific Design Automation Conference, 785-790, 2015 | 15 | 2015 |
| Accelerating adaptive background subtraction with GPU and CBEA architecture M Poremba, Y Xie, M Wolf 2010 IEEE Workshop On Signal Processing Systems, 305-310, 2010 | 15 | 2010 |
| Fine-granularity tile-level parallelism in non-volatile memory architecture with two-dimensional bank subdivision M Poremba, T Zhang, Y Xie Proceedings of the 53rd Annual Design Automation Conference, 1-6, 2016 | 11 | 2016 |
| Modular Routing Design for Chiplet-Based Systems. In 2018 ACM/IEEE 45th Annual International Symposium on Computer Architecture (ISCA). 726–738 J Yin, Z Lin, O Kayiran, M Poremba, MSB Altaf, NE Jerger, GH Loh | 10 | 2018 |
| Conditional prefetching MR Poremba, GH Loh US Patent 9,367,466, 2016 | 10 | 2016 |
| A Research Retrospective on AMD's Exascale Computing Journey GH Loh, MJ Schulte, M Ignatowski, V Adhinarayanan, S Aga, D Aguren, ... Proceedings of the 50th Annual International Symposium on Computer …, 2023 | 8 | 2023 |
| Hybrid cache MR Poremba, GH Loh US Patent 9,087,561, 2015 | 8 | 2015 |
| Installation cache MR Poremba, GH Loh US Patent 9,053,039, 2015 | 6 | 2015 |
| Approach for providing indirect addressing in memory modules MR Poremba, A Dutu, S Puthoor US Patent App. 17/561,406, 2023 | 3 | 2023 |
| Data compression and encryption based on translation lookaside buffer evictions JB Kotra, GH Loh, MR Poremba US Patent 11,507,519, 2022 | 3 | 2022 |
| Using predictions of outcomes of cache memory access requests for controlling whether a request generator sends memory access requests to a memory in parallel with cache memory … J Yin, Y Eckert, MR Poremba, SE Raasch, D Hunt US Patent 10,719,441, 2020 | 2 | 2020 |
