| DOST-ERDT Scholar, Electronics and Communications Engineering Department, De La Salle University, Manila, Philippines RB Caldo, RY Yap Control, Automation and Information Sciences (ICCAIS), 2013 International …, 2013 | 9* | 2013 |
| FPGA implementation of an indoor broadband power line channel emulator AE Dulay, R Sze, A Tan, YH Huang, R Yap, L Materum Information and Communications (ICIC), 2017 International Conference on, 218-223, 2017 | 6 | 2017 |
| Development of a Wideband PLC Channel Emulator with Random Noise Scenarios A Dulay, R Sze, A Tan, R Yap, L Materum Journal of Telecommunication, Electronic and Computer Engineering (JTEC) 10 …, 2018 | 3 | 2018 |
| Simulation of fuzzy logic controller for dc-dc buck and boost converter in three programming platforms RB Caldo, RY Yap Proceedings of the 2013 Asia Pacific Industrial Engineering and Management …, 2013 | 3 | 2013 |
| Improved noise robust automatic speech recognition system with spectral subtraction and minimum statistics algorithm implemented in FPGA JW Orillo, R Yap, E Sybingco TENCON 2012-2012 IEEE Region 10 Conference, 1-6, 2012 | 3 | 2012 |
| Hardware Modelling of a PLC Multipath Channel Transfer Function AE Dulay, R Yap, L Materum Journal of Telecommunication, Electronic and Computer Engineering (JTEC) 9 …, 2017 | 2 | 2017 |
| HARDWARE DESIGN AND IMPLEMENTATION OF GENETIC ALGORITHM FOR THE CONTROLLER OF A DC TO DC BOOST CONVERTER R Yap, K Lam, R Bugayong, E Hernandez, J De Guzman JURNAL TEKNOLOGI 78 (5-7), 117-122, 2016 | 2 | 2016 |
| Analog Realization of a Fractional-Order Element on 0.35μm CMOS Technology AC Abad, EA Gonzalez, RY Yap, L Dorcák viXra: 1401.0016, 2014 | 1 | 2014 |
| Driving philippine microelectronics education development with multi-university collaboration A Chua, AL Luna, CR Roque, L Alarcon, C Oppus, R Yap, EA Zafra, ... 2013 IEEE International Conference on Microelectronic Systems Education (MSE …, 2013 | 1 | 2013 |
| A Synthesizable VHDL Model of a Lossless Data Compression Circuit Using Run Length Encoding Algorithm AM Nagayo, R Yap DLSU engineering Journal 16 (2), 1-1, 2004 | 1 | 2004 |
| FPGA Library Based Design of a Hardware Model for Convolutional Neural Network with AUtomated Weight Compression using K-means Clustering L Yap, Roderick, Giron, Goldwin , Lanto, Leonard Miguel, Sta Maria, David ... International Journal of Advance Trends in Computer Science and Engineering …, 2019 | | 2019 |
| Hardware Implementation of Narrowband PLC Channel Emulator Based on Multipath Channel Model Using the Frequency Domain Approach AE Dulay, R Yap, NTRP del Castillo, KC San Juan, MC Tan Journal of Telecommunication, Electronic and Computer Engineering (JTEC) 9 …, 2017 | | 2017 |
| CMOS DESIGN OF 0.25 um CAPACITOR-LESS ALL DIGITAL CONTROLLER FOR A DC-DC BOOST CONVERTER J Telan, R Yap, F Castillo, A Gebana, M Ramos, A Santiago 8th AUN/SEED-Net Regional Conference on Electrical and Electronics Engineering, 2015 | | 2015 |
| Design and characterization of fully integrated low frequency, low voltage 0.25?? m CMOS clock generator circuit JC Konwat, R Yap TENCON 2014-2014 IEEE Region 10 Conference, 1-4, 2014 | | 2014 |
| Design and Development of Audit Central Data Bank at Ibiden Philippines, Inc.(IPI) RB Caldo, RY Yap TENCON 2012-2012 IEEE Region 10 Conference, 1-6, 2012 | | 2012 |
| An FPGA Based Multifunction Integrated Pipelined Coordinate Rotation Digital Computer D Santoso, R Yap | | 2007 |
| A PROGRAMMABLE SYSTOLIC ARRAY BASED MULTIPLIER DESIGN R Yap, A Ayroso, PM Aureo, MG De Leon | | |
