| Extensible and configurable RISC-V based virtual prototype V Herdt, D Große, HM Le, R Drechsler 2018 Forum on Specification & Design Languages (FDL), 5-16, 2018 | 82 | 2018 |
| RISC-V based virtual prototype: An extensible and configurable platform for the system-level V Herdt, D Große, P Pieper, R Drechsler Journal of Systems Architecture 109, 101756, 2020 | 73 | 2020 |
| Verifying SystemC using an intermediate verification language and symbolic simulation HM Le, D Große, V Herdt, R Drechsler Proceedings of the 50th Annual Design Automation Conference, 1-6, 2013 | 72 | 2013 |
| Verifying SystemC using intermediate verification language and stateful symbolic simulation V Herdt, HM Le, D Große, R Drechsler IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2018 | 48 | 2018 |
| Verifying Instruction Set Simulators using Coverage-guided Fuzzing* V Herdt, D Große, HM Le, R Drechsler 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), 360-365, 2019 | 47 | 2019 |
| Compiled symbolic simulation for SystemC V Herdt, HM Le, D Große, R Drechsler 2016 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 1-8, 2016 | 38 | 2016 |
| Early SoC security validation by VP-based static information flow analysis M Hassan, V Herdt, HM Le, D Große, R Drechsler 2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 400-407, 2017 | 37 | 2017 |
| Enhanced Virtual Prototyping RDV Herdt, D Große, R Drechsler Springer, 2021 | 36 | 2021 |
| Early concolic testing of embedded binaries with virtual prototypes: A RISC-V case study V Herdt, D Große, HM Le, R Drechsler Proceedings of the 56th Annual Design Automation Conference 2019, 1-6, 2019 | 32 | 2019 |
| Fast and Accurate Performance Evaluation for RISC-V using Virtual Prototypes* V Herdt, D Große, R Drechsler 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), 618-621, 2020 | 30 | 2020 |
| Towards Specification and Testing of RISC-V ISA Compliance⋆ V Herdt, D Große, R Drechsler 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), 995-998, 2020 | 28 | 2020 |
| Efficient cross-level testing for processor verification: A RISC-V case-study V Herdt, D Große, E Jentzsch, R Drechsler 2020 Forum for Specification and Design Languages (FDL), 1-7, 2020 | 27 | 2020 |
| Towards early validation of firmware-based power management using virtual prototypes: A constrained random approach V Herdt, HM Le, D Große, R Drechsler 2017 Forum on Specification and Design Languages (FDL), 1-8, 2017 | 24 | 2017 |
| Closing the RISC-V Compliance Gap: Looking from the Negative Testing Side* V Herdt, D Große, R Drechsler 2020 57th ACM/IEEE Design Automation Conference (DAC), 1-6, 2020 | 23 | 2020 |
| Towards formal verification of real-world SystemC TLM peripheral models-a case study HM Le, V Herdt, D Große, R Drechsler 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2016 | 23 | 2016 |
| Verifying SystemC using stateful symbolic simulation V Herdt, HM Le, R Drechsler Proceedings of the 52nd Annual Design Automation Conference, 1-6, 2015 | 22 | 2015 |
| The MicroRV32 framework: An accessible and configurable open source RISC-V cross-level platform for education and research S Ahmadi-Pour, V Herdt, R Drechsler Journal of Systems Architecture 133, 102757, 2022 | 21 | 2022 |
| On the application of formal fault localization to automated RTL-to-TLM fault correspondence analysis for fast and accurate VP-based error effect simulation-a case study V Herdt, HM Le, D Grobe, R Drechsler 2016 Forum on Specification and Design Languages (FDL), 1-8, 2016 | 21 | 2016 |
| Dynamic information flow tracking for embedded binaries using SystemC-based virtual prototypes P Pieper, V Herdt, D Große, R Drechsler 2020 57th ACM/IEEE Design Automation Conference (DAC), 1-6, 2020 | 20 | 2020 |
| Data flow testing for virtual prototypes M Hassan, V Herdt, HM Le, M Chen, D Große, R Drechsler Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017 …, 2017 | 20 | 2017 |
