| TEAM: Threshold adaptive memristor model S Kvatinsky, EG Friedman, A Kolodny, UC Weiser IEEE transactions on circuits and systems I: regular papers 60 (1), 211-221, 2012 | 524 | 2012 |
| Memristor-based material implication (imply) logic: Design principles and methodologies S Kvatinsky, G Satat, N Wald, EG Friedman, A Kolodny, UC Weiser IEEE Transaction on VLSI 22 (10), 2054 - 2066, 2014 | 342 | 2014 |
| MAGIC–memristor aided LoGIC S Kvatinsky, D Belousov, S Liman, G Satat, N Wald, EG Friedman, ... IEEE Transactions on Circuits and Systems II: Express Briefs 61 (11), 895 - 899, 2014 | 331 | 2014 |
| VTEAM: A general model for voltage-controlled memristors S Kvatinsky, M Ramadan, EG Friedman, A Kolodny IEEE Transactions on Circuits and Systems II: Express Briefs 62 (8), 786-790, 2015 | 283 | 2015 |
| MRL—Memristor ratioed logic S Kvatinsky, N Wald, G Satat, A Kolodny, UC Weiser, EG Friedman 2012 13th International Workshop on Cellular Nanoscale Networks and their …, 2012 | 185 | 2012 |
| Memristor-based multilayer neural networks with online gradient descent training D Soudry, D Di Castro, A Gal, A Kolodny, S Kvatinsky IEEE transactions on neural networks and learning systems 26 (10), 2408-2421, 2015 | 170 | 2015 |
| Logic design within memristive memories using memristor-aided loGIC (MAGIC) N Talati, S Gupta, P Mane, S Kvatinsky IEEE Transactions on Nanotechnology 15 (4), 635-650, 2016 | 146 | 2016 |
| Memristor-based IMPLY Logic Design Procedure S Kvatinsky, A Kolodny, UC Weiser, EG Friedman ICCD, 2011 | 124 | 2011 |
| Models of memristors for SPICE simulations S Kvatinsky, K Talisveyberg, D Fliter, A Kolodny, UC Weiser, EG Friedman 2012 IEEE 27th Convention of Electrical and Electronics Engineers in Israel, 1-5, 2012 | 90* | 2012 |
| Sneak-path constraints in memristor crossbar arrays Y Cassuto, S Kvatinsky, E Yaakobi 2013 IEEE International Symposium on Information Theory, 156-160, 2013 | 70 | 2013 |
| Logic operations in memory using a memristive Akers array Y Levy, J Bruck, Y Cassuto, EG Friedman, A Kolodny, E Yaakobi, ... Microelectronics Journal 45 (11), 1429-1437, 2014 | 69 | 2014 |
| The desired memristor for circuit designers S Kvatinsky, EG Friedman, A Kolodny, UC Weiser IEEE Circuits and Systems Magazine 13 (2), 17-22, 2013 | 63 | 2013 |
| Resistive associative processor L Yavits, S Kvatinsky, A Morad, R Ginosar IEEE Computer Architecture Letters 14 (2), 148-151, 2014 | 62 | 2014 |
| Dark memory and accelerator-rich system optimization in the dark silicon era A Pedram, S Richardson, M Horowitz, S Galal, S Kvatinsky IEEE Design & Test 34 (2), 39-50, 2016 | 52 | 2016 |
| Memristor for computing: Myth or reality? S Hamdioui, S Kvatinsky, G Cauwenberghs, L Xie, N Wald, S Joshi, ... Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017 …, 2017 | 51 | 2017 |
| A systematic approach to blocking convolutional neural networks X Yang, J Pu, BB Rister, N Bhagdikar, S Richardson, S Kvatinsky, ... arXiv preprint arXiv:1606.04209, 2016 | 36 | 2016 |
| Memristive logic: A framework for evaluation and comparison J Reuben, R Ben-Hur, N Wald, N Talati, AH Ali, PE Gaillardon, ... 2017 27th International Symposium on Power and Timing Modeling, Optimization …, 2017 | 33 | 2017 |
| SIMPLE MAGIC: Synthesis and in-memory mapping of logic execution for memristor-aided logic RB Hur, N Wald, N Talati, S Kvatinsky 2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 225-232, 2017 | 32 | 2017 |
| Memristive memory processing unit (MPU) controller for in-memory processing RB Hur, S Kvatinsky 2016 IEEE International Conference on the Science of Electrical Engineering …, 2016 | 29 | 2016 |
| Memory processing unit for in-memory processing RB Hur, S Kvatinsky 2016 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH …, 2016 | 28 | 2016 |
Avinoam KolodnyProfessor of Electrical Engineering, TechnionVerified email at ee.technion.ac.il
