Evgeny Bolotin
Evgeny Bolotin
NVIDIA Research
Verified email at nvidia.com
Cited by
Cited by
QNoC: QoS architecture and design process for network on chip
E Bolotin, I Cidon, R Ginosar, A Kolodny
Journal of systems architecture 50 (2-3), 105-128, 2004
Many-core vs. many-thread machines: Stay away from the valley
Z Guz, E Bolotin, I Keidar, A Kolodny, A Mendelson, UC Weiser
IEEE Computer Architecture Letters 8 (1), 25-28, 2009
Cost considerations in network on chip
E Bolotin, I Cidon, R Ginosar, A Kolodny
Integration 38 (1), 19-42, 2004
MCM-GPU: Multi-chip-module GPUs for continued performance scalability
A Arunkumar, E Bolotin, B Cho, U Milic, E Ebrahimi, O Villa, A Jaleel, ...
ACM SIGARCH Computer Architecture News 45 (2), 320-332, 2017
Scaling the power wall: a path to exascale
O Villa, DR Johnson, M Oconnor, E Bolotin, D Nellans, J Luitjens, ...
SC'14: Proceedings of the International Conference for High Performance …, 2014
The power of priority: NoC based distributed cache coherency
E Bolotin, Z Guz, I Cidon, R Ginosar, A Kolodny
First International Symposium on Networks-on-Chip (NOCS'07), 117-126, 2007
Efficient link capacity and QoS design for network-on-chip
Z Guz, I Walter, E Bolotin, I Cidon, R Ginosar, A Kolodny
Proceedings of the Design Automation & Test in Europe Conference 1, 1-6, 2006
Routing table minimization for irregular mesh NoCs
E Bolotin, I Cidon, R Ginosar, A Kolodny
2007 Design, Automation & Test in Europe Conference & Exhibition, 1-6, 2007
Anatomy of gpu memory system for multi-application execution
A Jog, O Kayiran, T Kesten, A Pattnaik, E Bolotin, N Chatterjee, ...
Proceedings of the 2015 International Symposium on Memory Systems, 223-234, 2015
A case for toggle-aware compression for GPU systems
G Pekhimenko, E Bolotin, N Vijaykumar, O Mutlu, TC Mowry, SW Keckler
2016 IEEE International Symposium on High Performance Computer Architecture …, 2016
Application-aware memory system for fair and efficient execution of concurrent gpgpu applications
A Jog, E Bolotin, Z Guz, M Parker, SW Keckler, MT Kandemir, CR Das
Proceedings of workshop on general purpose processing using GPUs, 1-8, 2014
Network delays and link capacities in application-specific wormhole NoCs
Z Guz, I Walter, E Bolotin, I Cidon, R Ginosar, A Kolodny
VLSI design 2007, 2007
Automatic hardware-efficient SoC integration by QoS network on chip
E Bolotin, A Morgenshtein, I Cidon, R Ginosar, A Kolodny
Proceedings of the 2004 11th IEEE International Conference on Electronics …, 2004
Beyond the socket: NUMA-aware GPUs
U Milic, O Villa, E Bolotin, A Arunkumar, E Ebrahimi, A Jaleel, A Ramirez, ...
Proceedings of the 50th Annual IEEE/ACM International Symposium on …, 2017
Combining HW/SW mechanisms to improve NUMA performance of multi-GPU systems
V Young, A Jaleel, E Bolotin, E Ebrahimi, D Nellans, O Villa
2018 51st Annual IEEE/ACM International Symposium on Microarchitecture …, 2018
Toggle-aware compression for GPUs
G Pekhimenko, E Bolotin, M O’Connor, O Mutlu, TC Mowry, SW Keckler
IEEE Computer Architecture Letters 14 (2), 164-168, 2015
Hybrid exclusive multi-level memory architecture with memory management
DG Feekes, S Raikin, B Fanning, J Ray, J Mandelblat, A Berkovits, ...
US Patent 9,734,079, 2017
Designing efficient heterogeneous memory architectures
E Bolotin, D Nellans, O Villa, M O'Connor, A Ramirez, SW Keckler
IEEE Micro 35 (4), 60-68, 2015
Exploring the limits of GPGPU scheduling in control flow bound applications
R Malits, E Bolotin, A Kolodny, A Mendelson
ACM Transactions on Architecture and Code Optimization (TACO) 8 (4), 1-22, 2012
Efficient routing in irregular topology NoCs
E Bolotin, I Cidon, R Ginosar, A Kolodny
Israel Institute of Technology, Technion Department of Electrical …, 2005
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