| Low power CMOS-based Hall sensor with simple structure using double-sampling delta-sigma ADC J Lee, Y Oh, S Oh, H Chae Sensors 20 (18), 5285, 2020 | 19 | 2020 |
| An 85 dB DR 4 MHz BW pipelined noise-shaping SAR ADC with 1–2 MASH structure S Oh, Y Oh, J Lee, K Kim, S Lee, J Kim, H Chae IEEE Journal of Solid-State Circuits 56 (11), 3424-3433, 2021 | 12 | 2021 |
| Sensitivity enhancement of a vertical-type CMOS Hall device for a magnetic sensor S Oh, BJ Jang, H Chae Journal of electromagnetic engineering and science 18 (1), 35-40, 2018 | 11 | 2018 |
| A 80dB DR 6MHz bandwidth pipelined noise-shaping SAR ADC with 1–2 MASH structure S Oh, Y Oh, J Lee, K Kim, S Lee, J Kim, H Chae 2020 IEEE Custom Integrated Circuits Conference (CICC), 1-4, 2020 | 9 | 2020 |
| An 8MHz 31.25 kS/s impedance-monitoring IC based on IF-sampling architecture with a band-pass delta-sigma ADC SJ Kweon, J Gil, C Park, S Oh, Y Jung, I Choi, S Cheon, HP Dang, JH Koo, ... 2021 Symposium on VLSI Circuits, 1-2, 2021 | 7 | 2021 |
| A high-efficiency single-mode dual-path buck-boost converter with reduced inductor current D Cho, H Cho, S Oh, Y Jung, S Ha, C Kim, M Je IEEE Journal of Solid-State Circuits 58 (3), 720-731, 2023 | 5 | 2023 |
| A 56fJ/Conversion-Step 178dB-FoMS Third-Order Hybrid CT-DT Δ∑ Capacitance-to-Digital Converter Y Jung, J Koo, S Oh, S Park, JH Suh, D Cho, M Je 2023 IEEE Custom Integrated Circuits Conference (CICC), 1-2, 2023 | 4 | 2023 |
| A single-mode dual-path buck-boost converter with reduced inductor current across all duty cases achieving 95.58% efficiency at 1A in boost operation D Cho, H Cho, S Oh, Y Jung, S Ha, C Kim, M Je 2022 IEEE Custom Integrated Circuits Conference (CICC), 1-2, 2022 | 4 | 2022 |
| Bandpass ΔΣ ADC using pipelined SAR ADC S Oh, K Kim, H Chae Electronics Letters 56 (10), 480-482, 2020 | 4 | 2020 |
| 4-Contact structure of vertical-type CMOS Hall device for 3-D magnetic sensor S Oh, D Hwang, H Chae IEICE Electronics Express 16 (4), 20180854-20180854, 2019 | 4 | 2019 |
| A synchronous-sampling impedance-readout IC with baseline-cancellation-based two-step conversion for fast neural electrical impedance tomography JH Suh, H Choi, Y Jung, S Oh, H Cho, N Koo, SJ Kim, C Bae, S Ha, M Je 2022 IEEE Asian Solid-State Circuits Conference (A-SSCC), 1-3, 2022 | 3 | 2022 |
| A 2.5 mW 12MHz-BW 69dB SNDR Passive Bandpass ΔΣ ADC with Highpass Noise-Shaping SAR Quantizers S Oh, S Park, Y Jung, J Koo, D Cho, S Ha, M Je 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and …, 2023 | 2 | 2023 |
| Conception and Simulation of a 2-Then-1-Bit/Cycle Noise-Shaping SAR ADC K Kim, S Oh, H Chae Electronics 10 (20), 2545, 2021 | 2 | 2021 |
| A 187dB FoMS 46fJ/Conv. 2nd-order Highpass Δ∑ Capacitance-to-Digital Converter Y Jung, S Oh, J Koo, S Park, JH Suh, D Cho, S Ha, M Je 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and …, 2023 | 1 | 2023 |
| A 16-channel Impedance-Readout IC with Synchronous Sampling and Baseline Cancellation for Fast Neural Electrical Impedance Tomography JH Suh, H Choi, Y Jung, S Oh, H Cho, N Koo, SJ Kim, C Bae, S Ha, M Je IEEE Solid-State Circuits Letters, 2023 | 1 | 2023 |
| 33.8 A Two-Electrode Bio-Impedance Readout IC with Complex-Domain Noise-Correlated Baseline Cancellation Supporting Sinusoidal Excitation SI Cheon, H Choi, G Yun, S Oh, JH Suh, S Ha, M Je 2024 IEEE International Solid-State Circuits Conference (ISSCC) 67, 556-558, 2024 | | 2024 |
| A 187-dB FoM Power-Efficient Second-Order Highpass Capacitance-to-Digital Converter Y Jung, S Oh, S Ha, M Je IEEE Journal of Solid-State Circuits, 2024 | | 2024 |
| A Load-Current-Regulating OLED Lamp Driver Using a Hybrid Step-Up Converter with 93.21% Efficiency at a High Conversion Ratio of 4.1 D Cho, H Shin, H Park, S Oh, T Lee, S Ha, C Kim, M Je ESSCIRC 2021-IEEE 47th European Solid State Circuits Conference (ESSCIRC …, 2021 | | 2021 |
Minkyu JeAssociate Professor, School of Electrical Engineering, KAISTVerified email at kaist.ac.kr
