| A 4Mb embedded SLC resistive-RAM macro with 7.2 ns read-write random-access time and 160ns MLC-access capability SS Sheu, MF Chang, KF Lin, CW Wu, YS Chen, PF Chiu, CC Kuo, ... 2011 IEEE International Solid-State Circuits Conference, 200-202, 2011 | 233 | 2011 |
| A 130 mV SRAM with expanded write and read margins for subthreshold applications MF Chang, SW Chang, PW Chou, WC Wu IEEE Journal of Solid-State Circuits 46 (2), 520-529, 2010 | 138 | 2010 |
| Low store energy, low VDDmin, 8T2R nonvolatile latch and SRAM with vertical-stacked resistive memory (memristor) devices for low power mobile applications PF Chiu, MF Chang, CW Wu, CH Chuang, SS Sheu, YS Chen, MJ Tsai IEEE Journal of Solid-State Circuits 47 (6), 1483-1496, 2012 | 129 | 2012 |
| A 65nm 1Mb nonvolatile computing-in-memory ReRAM macro with sub-16ns multiply-and-accumulate for binary DNN AI edge processors WH Chen, KX Li, WY Lin, KH Hsu, PY Li, CH Yang, CX Xue, EY Yang, ... 2018 IEEE International Solid-State Circuits Conference-(ISSCC), 494-496, 2018 | 121 | 2018 |
| Ambient energy harvesting nonvolatile processors: From circuit to system Y Liu, Z Li, H Li, Y Wang, X Li, K Ma, S Li, MF Chang, S John, Y Xie, J Shu, ... Proceedings of the 52nd Annual Design Automation Conference, 1-6, 2015 | 117 | 2015 |
| Fast-write resistive RAM (RRAM) for embedded applications SS Sheu, KH Cheng, MF Chang, PC Chiang, WP Lin, HY Lee, PS Chen, ... IEEE Design & Test of Computers 28 (1), 64-71, 2010 | 117 | 2010 |
| A low store energy, low VDDmin, nonvolatile 8T2R SRAM with 3D stacked RRAM devices for low power mobile applications PF Chiu, MF Chang, SS Sheu, KF Lin, PC Chiang, CW Wu, WP Lin, ... 2010 Symposium on VLSI Circuits, 229-230, 2010 | 108 | 2010 |
| A 65nm 4Kb algorithm-dependent computing-in-memory SRAM unit-macro with 2.3 ns and 55.8 TOPS/W fully parallel product-sum operation for binary DNN edge processors WS Khwa, JJ Chen, JF Li, X Si, EY Yang, X Sun, R Liu, PY Chen, Q Li, ... 2018 IEEE International Solid-State Circuits Conference-(ISSCC), 496-498, 2018 | 107 | 2018 |
| Circuit design challenges in embedded memory and resistive RAM (RRAM) for mobile SoC and 3D-IC MF Chang, PF Chiu, SS Sheu 16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011), 197-203, 2011 | 97 | 2011 |
| Differential sensing and TSV timing control scheme for 3D-IC WC Wu, YH Chen, MF Chang US Patent 7,969,193, 2011 | 90 | 2011 |
| 4.7 a 65nm reram-enabled nonvolatile processor with 6× reduction in restore time and 4× higher clock frequency using adaptive data retention and self-write-termination … Y Liu, Z Wang, A Lee, F Su, CP Lo, Z Yuan, CC Lin, Q Wei, Y Wang, ... 2016 IEEE International Solid-State Circuits Conference (ISSCC), 84-86, 2016 | 87 | 2016 |
| 24.1 a 1Mb multibit ReRAM computing-in-memory macro with 14.6 ns parallel MAC computing time for CNN based AI edge processors CX Xue, WH Chen, JS Liu, JF Li, WY Lin, WE Lin, JH Wang, WC Wei, ... 2019 IEEE International Solid-State Circuits Conference-(ISSCC), 388-390, 2019 | 85 | 2019 |
| A 0.5 V 4Mb logic-process compatible embedded resistive RAM (ReRAM) in 65nm CMOS using low-voltage current-mode sensing scheme with 45ns random read time MF Chang, CW Wu, CC Kuo, SJ Shen, KF Lin, SM Yang, YC King, CJ Lin, ... 2012 IEEE International Solid-State Circuits Conference, 434-436, 2012 | 84 | 2012 |
| A Large V/VDD Tolerant Zigzag 8T SRAM With Area-Efficient Decoupled Differential Sensing and Fast Write-Back Scheme JJ Wu, YH Chen, MF Chang, PW Chou, CY Chen, HJ Liao, MB Chen, ... IEEE Journal of Solid-State Circuits 46 (4), 815-827, 2011 | 80 | 2011 |
| 24.5 a twin-8T SRAM computation-in-memory macro for multiple-bit CNN-based machine learning X Si, JJ Chen, YN Tu, WH Huang, JH Wang, YC Chiu, WC Wei, SY Wu, ... 2019 IEEE International Solid-State Circuits Conference-(ISSCC), 396-398, 2019 | 79 | 2019 |
| An offset-tolerant fast-random-read current-sampling-based sense amplifier for small-cell-current nonvolatile memory MF Chang, SJ Shen, CC Liu, CW Wu, YF Lin, YC King, CJ Lin, HJ Liao, ... IEEE Journal of Solid-State Circuits 48 (3), 864-877, 2013 | 77 | 2013 |
| Nonvolatile memory design based on ferroelectric FETs S George, K Ma, A Aziz, X Li, A Khan, S Salahuddin, MF Chang, S Datta, ... Proceedings of the 53rd Annual Design Automation Conference, 1-6, 2016 | 73 | 2016 |
| Three-dimensional 4F2ReRAM cell with CMOS logic compatible process CH Wang, YH Tsai, KC Lin, MF Chang, YC King, CJ Lin, SS Sheu, ... 2010 International Electron Devices Meeting, 29.6. 1-29.6. 4, 2010 | 72 | 2010 |
| A high-speed 7.2-ns read-write random access 4-Mb embedded resistive RAM (ReRAM) macro using process-variation-tolerant current-mode read schemes MF Chang, SS Sheu, KF Lin, CW Wu, CC Kuo, PF Chiu, YS Yang, ... IEEE Journal of Solid-State Circuits 48 (3), 878-891, 2012 | 67 | 2012 |
| A Differential Data-Aware Power-Supplied (DAP) 8T SRAM Cell With Expanded Write/Read Stabilities for Lower VDDmin Applications MF Chang, JJ Wu, KT Chen, YC Chen, YH Chen, R Lee, HJ Liao, ... IEEE Journal of Solid-State Circuits 45 (6), 1234-1245, 2010 | 65 | 2010 |
Chih-Cheng HsiehNational Tsing Hua UniversityVerified email at ee.nthu.edu.tw
