| 2D materials: roadmap to CMOS integration C Huyghebaert, T Schram, Q Smets, TK Agarwal, D Verreck, S Brems, ... 2018 IEEE International Electron Devices Meeting (IEDM), 22.1. 1-22.1. 4, 2018 | 94 | 2018 |
| Ultra-scaled MOCVD MoS2 MOSFETs with 42nm contact pitch and 250µA/µm drain current Q Smets, G Arutchelvan, J Jussot, D Verreck, I Asselberghs, AN Mehta, ... 2019 IEEE International Electron Devices Meeting (IEDM), 23.2. 1-23.2. 4, 2019 | 81 | 2019 |
| MoS2 Functionalization with a Sub-nm Thin SiO2 Layer for Atomic Layer Deposition of High-κ Dielectrics H Zhang, G Arutchelvan, J Meersschaut, A Gaur, T Conard, H Bender, ... Chemistry of Materials 29 (16), 6772-6780, 2017 | 39 | 2017 |
| Impact of device scaling on the electrical properties of MoS2 field-effect transistors G Arutchelvan, Q Smets, D Verreck, Z Ahmed, A Gaur, S Sutar, J Jussot, ... Scientific reports 11 (1), 6610, 2021 | 37 | 2021 |
| Analysis of admittance measurements of MOS capacitors on CVD grown bilayer MoS2 A Gaur, D Chiappe, D Lin, D Cott, I Asselberghs, M Heyns, I Radu 2D Materials 6 (3), 035035, 2019 | 20 | 2019 |
| Integration of broken-gap heterojunction InAs/GaSb Esaki tunnel diodes on silicon K Bhatnagar, MP Caro, JS Rojas-Ramirez, R Droopad, PM Thomas, ... Journal of Vacuum Science & Technology B 33 (6), 2015 | 17 | 2015 |
| Performance Evaluation of In0.53Ga0.47As Esaki Tunnel Diodes on Silicon and InP Substrates P Thomas, M Filmer, A Gaur, DJ Pawlik, B Romanczyk, E Marini, ... IEEE Transactions on Electron Devices 62 (8), 2450-2456, 2015 | 16 | 2015 |
| Mapping Defect Density in MBE Grown Epitaxial Layers on Si Substrate Using Esaki Diode Valley Characteristics K Majumdar, P Thomas, WY Loh, PY Hung, K Matthews, D Pawlik, ... IEEE Transactions on Electron Devices 61 (6), 2049-2055, 2014 | 15 | 2014 |
| Demonstration of 2e12 cm−2 eV−1 2D-oxide interface trap density on back-gated MoS2 flake devices with 2.5 nm EOT A Gaur, Y Balaji, D Lin, C Adelmann, JV Houdt, M Heyns, D Mocuta, ... Microelectronic Engineering 178, 145-149, 2017 | 12 | 2017 |
| A MOS capacitor model for ultra-thin 2D semiconductors: the impact of interface defects and channel resistance A Gaur, T Agarwal, I Asselberghs, I Radu, M Heyns, D Lin 2D Materials 7 (3), 035018, 2020 | 10 | 2020 |
| Surface treatments to reduce leakage current in In0. 53Ga0. 47As pin diodes A Gaur, I Manwaring, MJ Filmer, PM Thomas, SL Rommel, K Bhatnagar, ... Journal of Vacuum Science & Technology B 33 (2), 2015 | 3 | 2015 |
| Understanding Charge Behaviour in a 2D Transition Metal Dichalcogenide MOS System A Gaur | 1 | 2020 |
| Beyond Silicon MOS: An Electrical Study on Interface and Gate Dielectrics with ac Admittance Techniques DHC Lin, A Vais, A Gaur, G Brammertz, AR Alian, L Nyns, S Sioncke, ... Materials Science and Technology, 1-16, 2019 | 1 | 2019 |
| Performance evaluation of broken gap Esaki tunnel diodes on Si and GaSb substrates PM Thomas, MJ Filmer, A Gaur, SL Rommel, K Bhatnagar, R Droopad Electronics Letters 52 (1), 73-75, 2016 | 1 | 2016 |
| Optimizing the MOS capacitor design to study large area 2D-oxide interface A Gaur, D Lin, D Chiappe, C Adelmann, J Van Houdt, D Mocuta, M Heyns, ... 48th IEEE Semiconductor Interface Specialists Conference-SISC, Date: 2017/01 …, 2017 | | 2017 |
| Fabrication and characterization of sub-micron In0. 53Ga0. 47As pin diodes A Gaur, M Filmer, P Thomas, K Bhatnagar, R Droopad, S Rommel Solid-State Electronics 111, 234-237, 2015 | | 2015 |
| Surface Treatments to Reduce Leakage Current in Homojunction In0.53Ga0.47As PIN Diodes for TFET Applications A Gaur Rochester Institute of Technology, 2015 | | 2015 |
Dennis Han Chung LinIMECVerified email at imec.be
