Antonis Papanikolaou
Antonis Papanikolaou
Hypertech SA
Η διεύθυνση ηλεκτρονικού ταχυδρομείου έχει επαληθευτεί στον τομέα
Παρατίθεται από
Παρατίθεται από
3-D technology assessment: Path-finding the technology/design sweet-spot
P Marchal, B Bougard, G Katti, M Stucchi, W Dehaene, A Papanikolaou, ...
Proceedings of the IEEE 97 (1), 96-107, 2009
Three dimensional system integration: IC stacking process and design
A Papanikolaou, D Soudris, R Radojcic
Springer Science & Business Media, 2010
Time and workload dependent device variability in circuit simulations
D Rodopoulos, SB Mahato, VV de Almeida Camargo, B Kaczer, ...
2011 IEEE International Conference on IC Design & Technology, 1-4, 2011
Method for exploring feasibility of an electronic system design
A Papanikolaou, M Miranda, P Roussel
US Patent 8,037,430, 2011
Variable tapered pareto buffer design and implementation allowing run-time configuration for low-power embedded SRAMs
H Wang, M Miranda, A Papanikolaou, F Catthoor, W Dehaene
IEEE transactions on very large scale integration (VLSI) systems 13 (10 …, 2005
Reliability issues in deep deep submicron technologies: Time-dependent variability and its impact on embedded system design
A Papanikolaou, H Wang, M Miranda, F Catthoor, W Dehaene
VLSI-SoC: Research Trends in VLSI and Systems on Chip, 119-141, 2008
A system-level methodology for fully compensating process variability impact of memory organizations in periodic applications
A Papanikolaou, F Lobmaier, H Wang, M Miranda, F Catthoor
Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware …, 2005
Design method for essentially digital systems and components thereof and essentially digital systems made in accordance with the method
F Catthoor, A Papanikolaou, K Maex
US Patent 7,124,377, 2006
Method and apparatus for designing and manufacturing electronic circuits subject to process variations
A Papanikolaou, M Miranda, F Catthoor, H Wang
US Patent 8,578,319, 2013
Energy/area/delay trade-offs in the physical design of on-chip segmented bus architecture
J Guo, A Papanikolaou, P Marchal, F Catthoor
Proceedings of the 2006 international workshop on System-level interconnect …, 2006
Enabling efficient system configurations for dynamic wireless applications using system scenarios
N Zompakis, A Papanikolaou, P Raghavan, D Soudris, F Catthoor
International journal of wireless information networks 20 (2), 140-156, 2013
Physical design implementation of segmented buses to reduce communication energy
J Guo, A Papanikolaou, P Marchal, F Catthoor
Asia and South Pacific Conference on Design Automation, 2006., 6 pp., 2006
Global interconnect trade-off for technology over memory modules to application level: case study
A Papanikolaou, M Miranda, F Catthoor, H Corporaal, H De Man, ...
Proceedings of the 2003 international workshop on System-level interconnect …, 2003
A global bus power optimization methodology for physical design of memory dominated systems by coupling bus segmentation and activity driven block placement
H Wang, A Papanikolaou, M Miranda, F Catthoor
ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE …, 2004
Fast design space exploration environment applied on noc's for 3d-stacked mpsoc's
A Richard, D Milojevic, F Robert, A Bartzas, A Papanikolaou, K Siozios, ...
23th International Conference on Architecture of Computing Systems 2010, 1-6, 2010
Propagating variability from technology to system level
B Dierickx, M Miranda, P Dobrovolny, F Kutscherauer, A Papanikolaou, ...
2007 International Workshop on Physics of Semiconductor Devices, 74-79, 2007
Resource activity aware system for determining a resource interconnection pattern within an essentially digital device and devices created therewith
A Papanikolaou, H Wang, J Guo, M Miranda, F Catthoor
US Patent 7,216,326, 2007
At tape-out: Can system yield in terms of timing/energy specifications be predicted?
A Papanikolaou, M Miranda, P Marchal, B Dierickx, F Catthoor
2007 IEEE Custom Integrated Circuits Conference, 773-778, 2007
Hypervised transient SPICE simulations of large netlists & workloads on multi-processor systems
G Lyras, D Rodopoulos, A Papanikolaou, D Soudris
2013 Design, Automation & Test in Europe Conference & Exhibition (DATE), 655-658, 2013
The analysis of system-level timing failures due to interconnect reliability degradation
J Guo, A Papanikolaou, M Stucchi, K Croes, Z Tökei, F Catthoor
IEEE Transactions on Device and Materials Reliability 8 (4), 652-663, 2008
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