Ruolong Lian
Ruolong Lian
LegUp Computing Inc.
Verified email at mail.utoronto.ca
Title
Cited by
Cited by
Year
From software to accelerators with LegUp high-level synthesis
A Canis, J Choi, B Fort, R Lian, Q Huang, N Calagar, M Gort, JJ Qin, ...
2013 International Conference on Compilers, Architecture and Synthesis for …, 2013
572013
The effect of compiler optimizations on high-level synthesis for FPGAs
Q Huang, R Lian, A Canis, J Choi, R Xi, S Brown, J Anderson
2013 IEEE 21st Annual International Symposium on Field-Programmable Custom …, 2013
562013
The effect of compiler optimizations on high-level synthesis-generated hardware
Q Huang, R Lian, A Canis, J Choi, R Xi, N Calagar, S Brown, J Anderson
ACM Transactions on Reconfigurable Technology and Systems (TRETS) 8 (3), 1-26, 2015
402015
Automating the design of processor/accelerator embedded systems with legup high-level synthesis
B Fort, A Canis, J Choi, N Calagar, R Lian, S Hadjis, YT Chen, M Hall, ...
2014 12th IEEE International Conference on Embedded and Ubiquitous Computing …, 2014
392014
FPGA-based CNN inference accelerator synthesized from multi-threaded C software
JH Kim, B Grady, R Lian, J Brothers, JH Anderson
2017 30th IEEE International System-on-Chip Conference (SOCC), 268-273, 2017
362017
Legup high-level synthesis
A Canis, J Choi, B Fort, B Syrowik, RL Lian, YT Chen, H Hsiao, J Goeders, ...
FPGAs for Software Programmers, 175-190, 2016
142016
Accelerating Memcached on AWS Cloud FPGAs
J Choi, R Lian, Z Li, A Canis, J Anderson
Proceedings of the 9th International Symposium on Highly-Efficient …, 2018
82018
From C to Blokus Duo with LegUp high-level synthesis
JC Cai, R Lian, M Wang, A Canis, J Choi, B Fort, E Hart, E Miao, Y Zhang, ...
2013 International Conference on Field-Programmable Technology (FPT), 486-489, 2013
62013
A unified software approach to specify pipeline and spatial parallelism in FPGA hardware
J Choi, RL Lian, S Brown, J Anderson
2016 IEEE 27th International Conference on Application-specific Systems …, 2016
52016
A framework for FPGA-based acceleration of neural network inference with limited numerical precision via high-level synthesis with streaming functionality
RL Lian
52016
High-level synthesis (HLS) method and apparatus to specify pipeline and spatial parallelism in computer hardware
J Choi, R Lian, AC Canis, JH Anderson
US Patent 10,579,762, 2020
12020
High-level synthesis (hls) method and apparatus to specify pipeline and spatial parallelism in computer hardware
J Choi, R Lian, AC Canis, JH Anderson
US Patent App. 16/714,571, 2020
2020
Additional Reviewers FCCM 2014
A Agne, R Ahmed, J Ambrose, J Anwer, S Bayliss, T Becker, ...
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