Yi-Shan Lu
Cited by
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Parallel triangle counting and k-truss identification using graph-centric methods
C Voegele, YS Lu, S Pai, K Pingali
2017 IEEE High Performance Extreme Computing Conference (HPEC), 1-7, 2017
Automatic generation of high-speed accurate TLM models for out-of-order pipelined bus
CK Lo, ML Li, LC Chen, YS Lu, RS Tsay, HY Huang, JC Yeh
ACM Transactions on Embedded Computing Systems (TECS) 13 (1s), 1-25, 2013
Cyclone: a static timing and power engine for asynchronous circuits
W Hua, YS Lu, K Pingali, R Manohar
2020 26th IEEE International Symposium on Asynchronous Circuits and Systems …, 2020
Unlocking fine-grain parallelism for AIG rewriting
V Possan, YS Lu, A Mishchenko, K Pingali, R Ribas, A Reis
2018 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 1-8, 2018
Can Parallel Programming Revolutionize EDA Tools?
YS Lu, K Pingali
Advanced Logic Synthesis, 21-41, 2018
A non-intrusive timing synchronization interface for hardware-assisted HW/SW co-simulation
YH Huang, YS Lu, HI Wu, RS Tsay
Proceedings of the 49th Annual Design Automation Conference, 127-132, 2012
Deadlock free synchronization synthesizer for must-happen-before relations in parallel programs and method thereof
YS Lu, HL Pai, MH Wu, RS Tsay
US Patent App. 13/455,659, 2013
A Digital Flow for Asynchronous VLSI Systems: Status Update
U Agarwal, S Ataei, J He, W Hua, YS Lu, S Maleki, Y Yang, K Pingali, ...
Toward a digital flow for asynchronous VLSI systems
S Ataei, J He, W Hua, YS Lu, S Maleki, Y Yang, K Pingali, R Manohar
ParallelClosure: A Parallel Design Optimizer for Timing Closure
YS Lu, W Hua, R Manohar, K Pingali
Parallel Tools for Asynchronous VLSI Systems
YS Lu, S Ataei, J He, W Hua, S Maleki, Y Yang, M Burtscher, K Pingali, ...
Automatic Generation for Efficient Software TLM at Multiple Abstraction Layers
MH Wu, YS Lu, WC Lee, CY Chuang, RS Tsay
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