Sagar Karandikar
Sagar Karandikar
Verified email at eecs.berkeley.edu - Homepage
Title
Cited by
Cited by
Year
The Rocket Chip Generator
K Asanovic, R Avizienis, J Bachrach, S Beamer, D Biancolin, C Celio, ...
EECS Department, University of California, Berkeley, Tech. Rep. UCB/EECS-2016-17, 2016
2982016
Network requirements for resource disaggregation
PX Gao, A Narayan, S Karandikar, J Carreira, S Han, R Agarwal, ...
12th USENIX Symposium on Operating Systems Design and Implementation (OSDI …, 2016
2162016
BOSS: Building Operating System Services.
S Dawson-Haggerty, A Krioukov, J Taneja, S Karandikar, G Fierro, ...
NSDI 13, 443-458, 2013
1472013
FireSim: FPGA-Accelerated Cycle-Exact Scale-Out System Simulation in the Public Cloud
S Karandikar, H Mao, D Kim, D Biancolin, A Amid, D Lee, N Pemberton, ...
45th International Symposium on Computer Architecture (ISCA 2018), 2018
852018
The rocket chip generator. EECS Department
K Asanovic, R Avizienis, J Bachrach, S Beamer, D Biancolin, C Celio, ...
University of California, Berkeley, Tech. Rep. UCB/EECS-2016-17, 2016
422016
FASED: FPGA-accelerated simulation and evaluation of DRAM
D Biancolin, S Karandikar, D Kim, J Koenig, A Waterman, J Bachrach, ...
Proceedings of the 2019 ACM/SIGDA International Symposium on Field …, 2019
182019
Chipyard: Integrated Design, Simulation, and Implementation Framework for Custom SoCs
A Amid, D Biancolin, A Gonzalez, D Grubb, S Karandikar, H Liew, ...
IEEE Micro, 2020
132020
The Hwacha Microarchitecture Manual, Version 3.8.
Y Lee, A Ou, C Schmidt, S Karandikar, H Mao, K Asanovic
EECS Department, University of California, Berkeley, Tech. Rep. UCB/EECS …, 2015
12*2015
FPGA Accelerated INDEL Realignment in the Cloud
L Wu, D Bruns-Smith, FA Nothaft, Q Huang, S Karandikar, J Le, A Lin, ...
2019 IEEE International Symposium on High Performance Computer Architecture …, 2019
102019
Hwacha Preliminary Evaluation Results, Version 3.8.
Y Lee, C Schmidt, S Karandikar, D Dabbelt, A Ou, K Asanovic
EECS Department, University of California, Berkeley, Tech. Rep. UCB/EECS …, 2015
7*2015
DESSERT: Debugging RTL Effectively with State Snapshotting for Error Replays across Trillions of cycles
D Kim, C Celio, S Karandikar, D Biancolin, J Bachrach, K Asanović
2018 28th International Conference on Field Programmable Logic and …, 2018
62018
Centrifuge: Evaluating full-system HLS-generated heterogenous-accelerator SoCs using FPGA-Acceleration
Q Huang, C Yarp, S Karandikar, N Pemberton, B Brock, L Ma, G Dai, ...
2019 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 1-8, 2019
52019
Vector Processors for Energy-Efficient Embedded Systems
D Dabbelt, C Schmidt, E Love, H Mao, S Karandikar, K Asanovic
Proceedings of the Third ACM International Workshop on Many-core Embedded …, 2016
52016
FirePerf: FPGA-Accelerated Full-System Hardware/Software Performance Profiling and Co-Design
S Karandikar, A Ou, A Amid, H Mao, R Katz, B Nikolić, K Asanović
25th International Conference on Architectural Support for Programming …, 2020
42020
Hardware Acceleration of Key-Value Stores
H Mao, S Karandikar, A Ou, S Basu
UC Berkeley CS262a Report, 2014
12014
Chipyard-An Integrated SoC Research and Implementation Environment
A Amid, D Biancolin, A Gonzalez, D Grubb, S Karandikar, H Liew, ...
2020 57th ACM/IEEE Design Automation Conference (DAC), 1-6, 2020
2020
Using FireSim to Enable Agile End-to-End RISC-V Computer Architecture Research
S Karandikar, D Biancolin, A Amid, N Pemberton, A Ou, R Katz, B Nikolic, ...
Third Workshop on Computer Architecture Research with RISC-V (CARRV 2019), 2019
2019
Debugging RISC-V Processors with FPGA-Accelerated RTL Simulation in the FPGA Cloud
D Kim, C Celio, S Karandikar, D Biancolin, J Bachrach, K Asanovic
Second Workshop on Computer Architecture Research with RISC-V (CARRV 2018), 2018
2018
FireSim: Cycle-accurate rack-scale system simulation using FPGAs in the public cloud
S Karandikar, H Mao, D Kim, D Biancolin, A Amid, D Lee, K Kovacs, ...
7th RISC-V Workshop, 2017
2017
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Articles 1–19