meng LI
meng LI
senior researcher @ imec
Η διεύθυνση ηλεκτρονικού ταχυδρομείου έχει επαληθευτεί στον τομέα imec.be
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Παρατίθεται από
Παρατίθεται από
Έτος
Design of rotated QAM mapper/demapper for the DVB-T2 standard
M Li, CA Nour, C Jego, C Douillard
Signal Processing Systems, 2009. SiPS 2009. IEEE Workshop on, 018-023, 2009
652009
Design and FPGA prototyping of a bit-interleaved coded modulation receiver for the DVB-T2 standard
M Li, CA Nour, C Jego, C Douillard
Signal Processing Systems (SIPS), 2010 IEEE Workshop on, 162-167, 2010
282010
An area and energy efficient half-row-paralleled layer LDPC decoder for the 802.11 AD standard
M Li, F Naessens, P Debacker, P Raghavan, C Desset, M Li, A Dejonghe, ...
Signal Processing Systems (SiPS), 2013 IEEE Workshop on, 112-117, 2013
242013
Efficient iterative receiver for bit-interleaved coded modulation according to the dvb-t2 standard
M Li, CA Nour, C Jégo, J Yang, C Douillard
Acoustics, Speech and Signal Processing (ICASSP), 2011 IEEE International …, 2011
182011
An energy efficient 18Gbps LDPC decoding processor for 802.11 ad in 28nm CMOS
M Li, JW Weijers, V Derudder, I Vos, M Rykunov, S Dupont, P Debacker, ...
Solid-State Circuits Conference (A-SSCC), 2015 IEEE Asian, 1-5, 2015
172015
Area and energy efficient 802.11 ad LDPC decoding processor
M Li, Y Lee, Y Huang, L Van der Perre
Electronics Letters 51 (4), 339-341, 2015
142015
A processor based multi-standard low-power LDPC engine for multi-Gbps wireless communication
M Li, F Naessens, M Li, P Debacker, C Desset, P Raghavan, A Dejonghe, ...
Global Conference on Signal and Information Processing (GlobalSIP), 2013 …, 2013
122013
A shuffled iterative bit-interleaved coded modulation receiver for the dvb-t2 standard: Design, implementation and fpga prototyping
M Li, CA Nour, C Jégo, J Yang, C Douillard
Signal Processing Systems (SIPS), 2011 IEEE Workshop on, 55-60, 2011
92011
Design, implementation and prototyping of an iterative receiver for bit-interleaved coded modulation system dedicated to DVB-T2
M Li
Télécom Bretagne, Université de Bretagne-Sud, 2012
72012
Computation-skip error resilient scheme for recursive CORDIC
Y Huang, M Li, C Li, P Debacker, L Van der Perre
Signal Processing Systems (SiPS), 2014 IEEE Workshop on, 1-6, 2014
52014
FPGA implementation of a shuffled iterative bit-interleaved coded modulation receiver
M Li, CA Nour, C Jégo, J Yang, C Douillard
ystem On Chip-System In Package (SOC-SIP), 2011
42011
An Energy-Efficient Reconfigurable ASIP Supporting Multi-mode MIMO Detection
U Ahmad, M Li, A Amin, M Li, L Van der Perre, R Lauwereins, S Pollin
Journal of Signal Processing Systems, 1-17, 2015
32015
Design of an efficient ldpc decoder for bit-interleaved coded modulation receivers
M Li, C Jego, CA Nour, C Douillard
Colloque national du groupe de recherches' System On Chip-System In Package …, 2010
32010
Towards approaching near-optimal MIMO detection performance ONAC-programmable baseband processor
U Ahmad, M Li, A Amin, M Li, L Van der Perre, R Lauwereins, S Pollin
Acoustics, Speech and Signal Processing (ICASSP), 2014 IEEE International …, 2014
12014
An area and energy efficient half-row-paralleled layer LDPC decoder for the 802.11AD standard
2013
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