Fault attacks on AES with faulty ciphertexts only T Fuhr, E Jaulmes, V Lomné, A Thillard 2013 Workshop on Fault Diagnosis and Tolerance in Cryptography, 108-118, 2013 | 115 | 2013 |
Combined fault and side-channel attack on protected implementations of aes T Roche, V Lomné, K Khalfallah International Conference on Smart Card Research and Advanced Applications, 65-83, 2011 | 80 | 2011 |
On the need of randomness in fault attack countermeasures-application to AES V Lomné, T Roche, A Thillard 2012 Workshop on Fault Diagnosis and Tolerance in Cryptography, 85-94, 2012 | 77 | 2012 |
How to estimate the success rate of higher-order side-channel attacks V Lomné, E Prouff, M Rivain, T Roche, A Thillard International Workshop on Cryptographic Hardware and Embedded Systems, 35-54, 2014 | 60 | 2014 |
Behind the scene of side channel attacks V Lomné, E Prouff, T Roche International Conference on the Theory and Application of Cryptology and …, 2013 | 52 | 2013 |
Statistical fault attacks on nonce-based authenticated encryption schemes C Dobraunig, M Eichlseder, T Korak, V Lomné, F Mendel International Conference on the Theory and Application of Cryptology and …, 2016 | 47 | 2016 |
Implementing lightweight block ciphers on x86 architectures R Benadjila, J Guo, V Lomné, T Peyrin International Conference on Selected Areas in Cryptography, 324-351, 2013 | 36 | 2013 |
Evaluating the robustness of secure triple track logic through prototyping R Soares, N Calazans, V Lomné, P Maurine, L Torres, M Robert Proceedings of the 21st annual symposium on Integrated circuits and system …, 2008 | 35 | 2008 |
Practical improvements of side-channel attacks on AES: feedback from the 2nd DPA contest C Clavier, JL Danger, G Duc, MA Elaabid, B Gérard, S Guilley, A Heuser, ... Journal of Cryptographic Engineering 4 (4), 259-274, 2014 | 30 | 2014 |
Evaluation on FPGA of triple rail logic robustness against DPA and DEMA V Lomné, P Maurine, L Torres, M Robert, R Soares, N Calazans 2009 Design, Automation & Test in Europe Conference & Exhibition, 634-639, 2009 | 28 | 2009 |
Formal framework for the evaluation of waveform resynchronization algorithms S Guilley, K Khalfallah, V Lomné, JL Danger IFIP International Workshop on Information Security Theory and Practices …, 2011 | 25 | 2011 |
Enhancing electromagnetic attacks using spectral coherence based cartography A Dehbaoui, V Lomne, P Maurine, L Torres, M Robert IFIP/IEEE International Conference on Very Large Scale Integration-System on …, 2009 | 18 | 2009 |
Side-channel attack against RSA key generation algorithms A Bauer, E Jaulmes, V Lomné, E Prouff, T Roche International Workshop on Cryptographic Hardware and Embedded Systems, 223-241, 2014 | 14 | 2014 |
Side channel attacks V Lomne, A Dehaboui, P Maurine, L Torres, M Robert Security trends for FPGAS, 47-72, 2011 | 14 | 2011 |
Collision-Correlation Attack against Some 1st-Order Boolean Masking Schemes in the Context of Secure Devices T Roche, V Lomné International Workshop on Constructive Side-Channel Analysis and Secure …, 2013 | 13 | 2013 |
Magnitude squared incoherence EM analysis for integrated cryptographic module localisation A Dehbaoui, V Lomne, P Maurine, L Torres Electronics letters 45 (15), 778-780, 2009 | 10 | 2009 |
Enhancing electromagnetic analysis using magnitude squared incoherence A Dehbaoui, V Lomné, T Ordas, L Torres, M Robert, P Maurine IEEE transactions on very large scale integration (VLSI) systems 20 (3), 573-577, 2011 | 8 | 2011 |
Cost-effective design strategies for securing embedded processors F Bruguier, P Benoit, L Torres, L Barthe, M Bourree, V Lomne IEEE Transactions on Emerging Topics in Computing 4 (1), 60-72, 2015 | 6 | 2015 |
Modeling time domain magnetic emissions of ICs V Lomné, P Maurine, L Torres, T Ordas, M Lisart, J Toublanc International Workshop on Power and Timing Modeling, Optimization and …, 2010 | 6 | 2010 |
Modeling time domain magnetic emissions of ICs V Lomné, P Maurine, L Torres, T Ordas, M Lisart, J Toublanc International Workshop on Power and Timing Modeling, Optimization and …, 2010 | 6 | 2010 |