Shahed Anwar
Cited by
Cited by
A Survey on Energy Efficient Routing Techniques in Wireless Sensor Network
MA Rahman, S Anwar, MI Pramanik, MF Rahman
ICACT 2013, 2013
Queue management based congestion control in wireless body sensor network
M Samiullah, SM Abdullah, AFMIH Bappi, S Anwar
2012 International Conference on Informatics, Electronics & Vision (ICIEV …, 2012
Realization of reversible logic in DNA computing
A Sarker, T Ahmed, SMM Rashid, S Anwar, L Jaman, N Tara, MM Alam, ...
2011 IEEE 11th International Conference on Bioinformatics and Bioengineering …, 2011
Design of a reversible random access memory
N Huda, S Anwar, L Jamal, HMH Babu
Dhaka University Journal of Applied Science and Engineering 2 (1), 31-38, 2011
Enhanced qlrs-apm: A new proposal for enhancing local route repair in mobile ad hoc networks
MA Rahman, S Anwar
Recent Advances in Computer Science and Information Engineering: Volume 4, 91-99, 2012
Efficient Approach to design Reversible Fault Tolerant Cyclic Redundancy Check Circuit
SK Mitra, T Sultana, S Anwar, AR Chowdhury
Proceedings of the 2nd International Conference on Signals, Systems …, 2011
An advanced minimization technique for multiple valued multiple output logic expressions using LUT and realization using current mode CMOS
MS Shahriar, AR Mustafa, CF Ahmed, AA Ferdaus, ANM Zaheduzzaman, ...
8th Euromicro Conference on Digital System Design (DSD'05), 122-126, 2005
A Simulation Study of Walks in Large Social Graphs
S Anwar
University of Victoria, 2015
Modified QLRS-APM: A Proposal to Avoid Initiating Route Error Messages to Source in Mobile Ad Hoc Networks
R Shahariar, S Anwar
The Dhaka University Journal of Science 62 (1), 59-64, 2014
A New Proposal for Choosing a Deflection Link in a Deflection Network
MA Rahman, MT Hossain, S Anwar
2008 11th International Conference on Computer and Information Technology …, 2008
Fault Tolerance: A means to provide reliable computing systems
LKMS Shahed Anwar
9th World Multiconference on Systemics, Cybernetics and Informatics (WMSCI 2005), 2005
Efficient Design of Check Circuit to detect Multiple Cell Errors in Reversible Logic Synthesis
SK Mitra, S Anwar, AR Chowdhury
Online Testable Fault Tolerant Full Adder in Reversible Logic Synthesis
SK Mitra, MF Hossain, S Anwar, AR Chowdhury
The system can't perform the operation now. Try again later.
Articles 1–13