prashant majhi
prashant majhi
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Cited by
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Forming a type I heterostructure in a group IV semiconductor
CO Chui, P Majhi, W Tsai, JT Kavalieros
US Patent 7,435,987, 2008
Si tunnel transistors with a novel silicided source and 46mV/dec swing
K Jeon, WY Loh, P Patel, CY Kang, J Oh, A Bowonder, C Park, CS Park, ...
2010 Symposium on VLSI Technology, 121-122, 2010
Dipole model explaining high-/metal gate field effect transistor threshold voltage tuning
PD Kirsch, P Sivasubramani, J Huang, CD Young, MA Quevedo-Lopez, ...
Applied Physics Letters 92 (9), 092901, 2008
Wafer-scale, sub-5 nm junction formation by monolayer doping and conventional spike annealing
JC Ho, R Yerushalmi, G Smith, P Majhi, J Bennett, J Halim, VN Faifer, ...
Nano Letters 9 (2), 725-730, 2009
InGaAs metal-oxide-semiconductor capacitors with gate dielectric grown by atomic-layer deposition
N Goel, P Majhi, CO Chui, W Tsai, D Choi, JS Harris
Applied physics letters 89 (16), 163517, 2006
Work function engineering using lanthanum oxide interfacial layers
HN Alshareef, M Quevedo-Lopez, HC Wen, R Harris, P Kirsch, P Majhi, ...
Applied physics letters 89 (23), 232103, 2006
Effective work function of Pt, Pd, and Re on atomic layer deposited
D Gu, SK Dey, P Majhi
Applied Physics Letters 89 (8), 082907, 2006
Prospect of tunneling green transistor for 0.1 V CMOS
C Hu, P Patel, A Bowonder, K Jeon, SH Kim, WY Loh, CY Kang, J Oh, ...
2010 International Electron Devices Meeting, 16.1. 1-16.1. 4, 2010
Nanoscale doping of InAs via sulfur monolayers
JC Ho, AC Ford, YL Chueh, PW Leu, O Ergen, K Takei, G Smith, P Majhi, ...
Applied Physics Letters 95 (7), 072108, 2009
Three-dimensional (3D) memory with shared control circuitry using wafer-to-wafer bonding
R Fastow, K Hasnat, P Majhi, O Jungroth
US Patent 10,651,153, 2020
based metal oxide semiconductor capacitors with atomic layer deposition gate oxide demonstrating low gate leakage current and equivalent oxide …
S Koveshnikov, N Goel, P Majhi, H Wen, MB Santos, S Oktyabrsky, ...
Applied Physics Letters 92 (22), 222904, 2008
Intrinsic characteristics of high-k devices and implications of fast transient charging effects (FTCE)
BH Lee, CD Young, R Choi, JH Sim, G Bersuker, CY Kang, R Harris, ...
IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004 …, 2004
Characteristics and mechanism of tunable work function gate electrodes using a bilayer metal structure on SiO/sub 2/and HfO/sub 2
CH Lu, GMT Wong, MD Deal, W Tsai, P Majhi, CO Chui, MR Visokay, ...
IEEE electron device letters 26 (7), 445-447, 2005
Transistors and methods of manufacture thereof
H Luan, P Majhi
US Patent 7,361,538, 2008
High-indium-content InGaAs metal-oxide-semiconductor capacitor with amorphous gate dielectric
N Goel, P Majhi, W Tsai, M Warusawithana, DG Schlom, MB Santos, ...
Applied Physics Letters 91 (9), 093509, 2007
Metal gate work function engineering using interfacial layers
HN Alshareef, HF Luan, K Choi, HR Harris, HC Wen, MA Quevedo-Lopez, ...
Applied Physics Letters 88 (11), 112114, 2006
Addressing the gate stack challenge for high mobility InxGa1-xAs channels for NFETs
N Goel, D Heh, S Koveshnikov, I Ok, S Oktyabrsky, V Tokranov, ...
2008 IEEE International Electron Devices Meeting, 1-4, 2008
Self-aligned -channel metal-oxide-semiconductor field effect transistor on high-indium-content and InP using physical vapor deposition and …
IJ Ok, H Kim, M Zhang, F Zhu, S Park, J Yum, H Zhao, D Garcia, P Majhi, ...
Applied Physics Letters 92 (20), 202903, 2008
Electrical reliability aspects of HfO2 high-k gate dielectrics with TaN metal gate electrodes under constant voltage stress
S Chatterjee, Y Kuo, J Lu, JY Tewg, P Majhi
Microelectronics Reliability 46 (1), 69-76, 2006
Band-Engineered Low PMOS VT with High-K/Metal Gates Featured in a Dual Channel CMOS Integration Scheme
HR Harris, P Kalra, P Majhi, M Hussain, D Kelly, J Oh, D He, C Smith, ...
2007 IEEE Symposium on VLSI Technology, 154-155, 2007
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