| Arrangement and method for controlling power modes of hardware resources A Terechko, M Garg US Patent 7,500,126, 2009 | 109 | 2009 |
| Parallel H. 264 decoding on an embedded multicore processor A Azevedo, C Meenderinck, B Juurlink, A Terechko, J Hoogerbrugge, ... High Performance Embedded Architectures and Compilers: Fourth International …, 2009 | 77 | 2009 |
| Register file gating to reduce microprocessor power dissipation A Terechko, M Garg US Patent 7,539,879, 2009 | 67 | 2009 |
| Inter-cluster communication models for clustered VLIW processors A Terechko, E Le Thenaff, M Garg, J Van Eijndhoven, H Corporaal The Ninth International Symposium on High-Performance Computer Architecture …, 2003 | 59 | 2003 |
| A hardware task scheduler for embedded video processing G Al-Kadi, AS Terechko High Performance Embedded Architectures and Compilers: Fourth International …, 2009 | 56 | 2009 |
| A multithreaded multicore system for embedded media processing J Hoogerbrugge, A Terechko Transactions on high-performance embedded architectures and compilers III …, 2011 | 51 | 2011 |
| A look-ahead task management unit for embedded multi-core architectures M Själander, A Terechko, M Duranton 2008 11th EUROMICRO Conference on Digital System Design Architectures …, 2008 | 49 | 2008 |
| Runtime software-based self-test with mutual inter-core checking AS Terechko, GHO Daalderop, J van Doorn, H Raaijmakers US Patent 10,628,275, 2020 | 38 | 2020 |
| Clustered ilp processor and a method for accessing a bus in a clustered ilp processor OPDR Moreira, A Terechko, V Van Acht US Patent App. 10/540,409, 2006 | 28 | 2006 |
| Evaluation of speed and area of clustered VLIW processors A Terechko, M Garg, H Corporaal 18th International Conference on VLSI Design held jointly with 4th …, 2005 | 24 | 2005 |
| A highly scalable parallel implementation of H. 264 A Azevedo, B Juurlink, C Meenderinck, A Terechko, J Hoogerbrugge, ... Transactions on High-Performance Embedded Architectures and Compilers …, 2009 | 21 | 2009 |
| Inter-cluster communication in vliw architectures AS Terechko, H Corporaal ACM Transactions on Architecture and Code Optimization (TACO) 4 (2), 11-es, 2007 | 21 | 2007 |
| Data processing system and method for monitoring the cache coherence of processing units AS Terechko, JM Nageswaran US Patent App. 11/577,592, 2009 | 19 | 2009 |
| Cluster assignment of global values for clustered VLIW processors A Terechko, E Le Thénaff, H Corporaal Proceedings of the 2003 international conference on Compilers, architecture …, 2003 | 19 | 2003 |
| Parallel three-dimensional recursive search (3DRS) meandering algorithm G Al-Kadi, AS Terechko, J Hoogerbrugge, AK Riemens, K Brink US Patent 8,265,160, 2012 | 18 | 2012 |
| A retargetable fault injection framework for safety validation of autonomous vehicles Y Fu, A Terechko, T Bijlsma, PJL Cuijpers, J Redegeld, AO Örs 2019 IEEE International Conference on Software Architecture Companion (ICSA …, 2019 | 17 | 2019 |
| Clustered VLIW architectures: a quantitative approach AS Terechko | 17 | 2007 |
| Cache-coherent heterogeneous multiprocessing as basis for streaming applications J van Eijndhoven, J Hoogerbrugge, MN Jayram, P Stravers, A Terechko Dynamic and robust streaming in and between connected consumer-electronic …, 2005 | 17 | 2005 |
| A distributed safety mechanism using middleware and hypervisors for autonomous vehicles T Bijlsma, A Buriachevskyi, A Frigerio, Y Fu, K Goossens, AO Örs, ... 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2020 | 14 | 2020 |
| PRMDL: a machine description language for clustered VLIW architectures. AS Terechko, EJD Pol, JTJ van Eijndhoven date, 821, 2001 | 14 | 2001 |
