| Network-on-chip hardware accelerators for biological sequence alignment S Sarkar, GR Kulkarni, PP Pande, A Kalyanaraman IEEE Transactions on Computers 59 (1), 29-41, 2009 | 68 | 2009 |
| Hardware accelerators for biocomputing: A survey S Sarkar, T Majumder, A Kalyanaraman, PP Pande Proceedings of 2010 IEEE International Symposium on Circuits and Systems …, 2010 | 57 | 2010 |
| Power-aware multi-core simulation for early design stage hardware/software co-optimization W Heirman, S Sarkar, TE Carlson, I Hur, L Eeckhout Proceedings of the 21st international conference on Parallel architectures …, 2012 | 47 | 2012 |
| NoC-based hardware accelerator for breakpoint phylogeny T Majumder, S Sarkar, PP Pande, A Kalyanaraman IEEE Transactions on Computers 61 (6), 857-869, 2011 | 13 | 2011 |
| Multiple clock domain synchronization for network on chip architectures J Nyathi, S Sarkar, PP Pande 2007 IEEE International SOC Conference, 291-294, 2007 | 12 | 2007 |
| Small Transactions with Sustainable Incentives F Pianese, M Signorini, S Sarkar 2018 9th IFIP International Conference on New Technologies, Mobility and …, 2018 | 5 | 2018 |
| Using fast and accurate simulation to explore hardware/software trade-offs in the multi-core era W Heirman, T Carlson, S Sarkar, P Ghysels, W Vanroose, L Eeckhout 2011 International conference on Parallel Computing (ParCo 2011), 2011 | 4 | 2011 |
| An optimized NoC architecture for accelerating TSP kernels in breakpoint median problem T Majumder, S Sarkar, P Pande, A Kalyanaraman ASAP 2010-21st IEEE International Conference on Application-specific Systems …, 2010 | 4 | 2010 |
| School Of Electrical Engineering and Computer Science S Sarkar, T Majumder, A Kalyanaraman, PP Pande Washington State University, Pullman, USA HealthGrid.“WISDOM”< http://wiki …, 0 | 2 | |
| Millimeter-wave in-package: tackling the system-in-package interconnection paradigm S Sarkar, GJ Stockman, B Francois https://arxiv.org/abs/2003.12262, 2020 | | 2020 |
| A Reconfigurable Architecture for Posit Arithmetic S Sarkar, P Murugappa, M Dev Gomony 22nd Euromicro Conference on Digital System Design, {DSD} 2019., 82--87, 2019 | | 2019 |
| BLOCKCHAIN-BASED ELECTRONIC TRANSFER METHOD AND SYSTEM F PIANESE, S SOURADIP EP Patent EP3,376,453, 2018 | | 2018 |
| SYSTEM FOR STORING GRAPH DATA STRUCTURES S SARKAR, F PIANESE EP Patent EP3,293,926, 2018 | | 2018 |
| Quater-Imaginary Base for Complex Number Arithmetic Circuits S Sarkar, MD Gomony Design Automation and Test in Europe (DATE) 17746177, 2018 | | 2018 |
| METHOD AND SYSTEM FOR PARALLEL QUERY USING BITMASK MULTICAST S SARKAR, MDEV GOMONY, A DE LIND VAN WIJNGAARDEN, ... EP Patent EP3,223,172, 2017 | | 2017 |
| Power aware early design stage hardware software co-optimization S Sarkar, W Heirman, T Carlson, L Eeckhout 8th International Summer School on Advanced Computer Architecture and …, 2012 | | 2012 |
| Network on chip based hardware accelerators for computational biology S Sarkar | | 2010 |
| Multiple Clock Domain Synchronization for Network on Chips S Sarkar Washington State University, 2007 | | 2007 |
| Multiple Clock Domain Synchronization for Network on Chips. December 2007 S Sarkar Washington State University thesis for Master of Science in Computer …, 2007 | | 2007 |
Partha PandeWashington State UniversityVerified email at wsu.edu
