Sorin Cotofana
Sorin Cotofana
Quantum & Computer Engineering, Delft University of Technology
Verified email at tudelft.nl - Homepage
TitleCited byYear
The MOLEN ρμ-coded processor
S Vassiliadis, S Wong, S Cotöfană
International Conference on Field Programmable Logic and Applications, 275-285, 2001
1392001
A linear threshold gate implementation in single electron technology
C Lageweg, S Cotofana, S Vassiliadis
Proceedings IEEE Computer Society Workshop on VLSI 2001. Emerging …, 2001
1282001
A sum of absolute differences implementation in FPGA hardware
S Wong, S Vassiliadis, S Cotofana
Proceedings. 28th Euromicro Conference, 183-188, 2002
922002
Single electron encoded latches and flip-flops
C Lageweg, S Cotofana, S Vassiliadis
IEEE Transactions on Nanotechnology 3 (2), 237-248, 2004
812004
Determining a coverage mask for a pixel
D Crisu, S Cotofana, S Vassiliadis, P Liuha
US Patent 7,006,110, 2006
802006
A unified aging model of NBTI and HCI degradation towards lifetime reliability management for nanoscale MOSFET circuits
Y Wang, S Cotofana, L Fang
Proceedings of the 2011 IEEE/ACM International Symposium on Nanoscale …, 2011
732011
Addition related arithmetic operations via controlled transport of charge
S Cotofana, C Lageweg, S Vassiliadis
IEEE Transactions on Computers 54 (3), 243-256, 2005
612005
2-1 addition and related arithmetic operations with threshold logic
S Vassilladis, S Contofana, K Bertels
Computers, IEEE Transactions on 45 (9), 1062-1067, 1996
551996
Field-programmable custom computing machines-a taxonomy
M Sima, S Vassiliadis, S Cotofana, JTJ van Eijndhoven, K Vissers
International Conference on Field Programmable Logic and Applications, 79-88, 2002
492002
Static buffered set based logic gates
C Lageweg, S Cotofana, S Vassiliadis
Proceedings of the 2nd IEEE Conference on Nanotechnology, 491-494, 2002
492002
A full adder implementation using SET based linear threshold gates
C Lageweg, S Cotofana, S Vassiliadis
9th International Conference on Electronics, Circuits and Systems 2, 665-668, 2002
402002
Periodic symmetric functions, serial addition, and multiplication with neural networks
S Cotofana, S Vassiliadis
IEEE Transactions on Neural Networks 9 (6), 1118-1128, 1998
391998
An 8x8 IDCT Implementation on an FPGA-augmented TriMedia
M Sima, S Cotofana, JTJ van Eijndhoven, S Vassiliadis, K Vissers
The 9th Annual IEEE Symposium on Field-Programmable Custom Computing …, 2001
382001
Low weight and fan-in neural networks for basic arithmetic operations
S Cotofana, S Vassiliadis
15th IMACS World Congress, 227-232, 1997
361997
Statistical reliability analysis of NBTI impact on FinFET SRAMs and mitigation technique using independent-gate devices
Y Wang, SD Cotofana, L Fang
2012 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH …, 2012
332012
An O (n) residue number system to mixed radix conversion technique
KA Gbolagade, SD Cotofana
2009 IEEE International Symposium on Circuits and Systems, 521-524, 2009
332009
An analysis of internal parameter variations effects on nanoscaled gates
F Martorell, SD Cotofana, A Rubio
IEEE transactions on nanotechnology 7 (1), 24-33, 2008
312008
Microcode processing: Positioning and directions
S Vassiliadis, S Wong, S Cotofana
IEEE Micro 23 (4), 21-30, 2003
312003
An improved RNS reverse converter for the {22n+1−1, 2n, 2n−1} moduli set
KA Gbolagade, R Chaves, L Sousa, SD Cotofana
Proceedings of 2010 IEEE International Symposium on Circuits and Systems …, 2010
302010
Future directions of programmable and reconfigurable embedded processors
S Wong, S Vassiliadis, S Cotofana
Domain-specific processors: systems, architectures, modeling, and simulation …, 2004
292004
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