Tao Jiang
Tao Jiang
Senior Staff Engineer, Qualcomm
Verified email at
Cited by
Cited by
A Single-Channel, 1.25-GS/s, 6-bit, 6.08-mW Asynchronous Successive-Approximation ADC With Improved Feedback Delay in 40-nm CMOS
T Jiang, W Liu, FY Zhong, C Zhong, K Hu, PY Chiang
Solid-State Circuits, IEEE Journal of 47 (10), 2444 - 2453, 2012
A 0.6 mW/Gb/s, 6.4–7.2 Gb/s serial link receiver using local injection-locked ring oscillators in 90 nm CMOS
K Hu, T Jiang, J Wang, F O'Mahony, PY Chiang
IEEE Journal of Solid-State Circuits 45 (4), 899-908, 2010
Single-channel, 1.25-GS/s, 6-bit, loop-unrolled asynchronous SAR-ADC in 40nm-CMOS
T Jiang, W Liu, FY Zhong, C Zhong, PY Chiang
Custom Integrated Circuits Conference (CICC), 2010 IEEE, 1-4, 2010
Time-interleaved track-and-hold circuit using distributed global sine-wave clock
T Jiang, PY Chiang, FY Zhong
US Patent 8,487,795, 2013
0.16-0.25 pJ/bit, 8 Gb/s near-threshold serial link receiver with super-harmonic injection-locking
K Hu, R Bai, T Jiang, C Ma, A Ragab, S Palermo, PY Chiang
IEEE journal of solid-state circuits 47 (8), 1842-1853, 2012
A 0.6 mW/Gbps, 6.4–8.0 Gbps serial link receiver using local injection-locked ring oscillators in 90nm CMOS
K Hu, T Jiang, J Wang, F O'Mahony, PY Chiang
2009 Symposium on VLSI Circuits, 46-47, 2009
Comparison of on-die global clock distribution methods for parallel serial links
K Hu, T Jiang, P Chiang
2009 IEEE International Symposium on Circuits and Systems (ISCAS), 1843-1846, 2009
Sense amplifier power and delay characterization for operation under low-Vdd and low-voltage clock swing
T Jiang, PY Chiang
Circuits and Systems, 2009. ISCAS 2009. IEEE International Symposium on, 181-184, 2009
Low-power 8Gb/s near-threshold serial link receivers using super-harmonic injection locking in 65nm CMOS
K Hu, T Jiang, S Palermo, PY Chiang
Custom Integrated Circuits Conference (CICC), 2011 IEEE, 1-4, 2011
Design techniques for low-power multi-GS/s analog-to-digital converters
T Jiang
Oregon State University, 2013
14.4-GS/s, 5-bit, 50mW time-interleaved ADC with distributed track-and-hold and sampling instant synchronization for ADC-based SerDes
T Jiang, PY Chiang
2015 IEEE International Wireless Symposium (IWS 2015), 1-4, 2015
Energy-efficient, decision feedback equalization Using SAR-like capacitive charge summation
T Jiang, P Chiang
Proceedings of 2010 International Symposium on VLSI Design, Automation and …, 2010
Wideband transmitter with high-frequency signal peaking
Z Chen, KL Arcudia, T Jiang
US Patent 9,497,049, 2016
A low-power, capacitively-divided, ring oscillator with digitally adjustable voltage swing
T Jiang, K Hu, PY Chiang
Proceedings of Technical Program of 2012 VLSI Design, Automation and Test, 1-4, 2012
Multiple Points Curvature Compensated Bandgap Voltage Reference
TJ Huazhong Yang
CN Patent 2,006,101,142,823, 2008
The system can't perform the operation now. Try again later.
Articles 1–15