loic lagadec
loic lagadec
ENSTA Bretagne, UMR 6285
Verified email at - Homepage
Cited by
Cited by
Placing, routing, and editing virtual FPGAs
L Lagadec, D Lavenier, E Fabiani, B Pottier
International Conference on Field Programmable Logic and Applications, 357-366, 2001
Abstraction, modélisation et outils de CAO pour les circuits intégrés reconfigurables
L Lagadec
PhD thesis, Université de Rennes 1, 2000
Object-oriented meta tools for reconfigurable architectures
L Lagadec, B Pottier
Reconfigurable Technology: FPGAs for Computing and Applications II 4212, 69-79, 2000
An LUT-based high level synthesis framework for reconfigurable architectures
L Lagadec, B Pottier, O Villellas-Guillen
Domain-Specific Processors: Systems, Architectures, Modeling, and Simulation …, 2003
A design approach to automatically synthesize ansi-c assertions during high-level synthesis of hardware accelerators
MB Hammouda, P Coussy, L Lagadec
2014 IEEE International Symposium on Circuits and Systems (ISCAS), 165-168, 2014
A dominating tree based leader election algorithm for smart cities IoT infrastructure
N Kadjouh, A Bounceur, M Bezoui, ME Khanouche, R Euler, ...
Mobile Networks and Applications, 1-14, 2020
Extended overlay architectures for heterogeneous FPGA cluster management
M Najem, T Bollengier, JC Le Lann, L Lagadec
Journal of Systems Architecture 78, 1-14, 2017
Software-like debugging methodology for reconfigurable platforms
L Lagadec, D Picard
2009 IEEE International Symposium on Parallel & Distributed Processing, 1-4, 2009
An extended modeling approach for marine/deep-sea observatory
CG Aoun, L Lagadec, M Habes
International Conference on Advanced Machine Learning Technologies and …, 2022
A surface runoff mapping method for optimizing risk assessment on railways
LR Lagadec, L Moulin, I Braud, B Chazelle, P Breil
Safety science 110, 253-267, 2018
Les observatoires du trait de côte en France métropolitaine et dans les DOM
S Suanez, M Garcin, T Bulteau, M Rouan, L Lagadec, L David
Echogeo, 2012
Benchmarking quantized neural networks on FPGAs with FINN
Q Ducasse, P Cotret, L Lagadec, R Stewart
arXiv preprint arXiv:2102.01341, 2021
Regular 2d nasic-based architecture and design space exploration
C Teodorov, P Narayanan, L Lagadec, C Dezan
2011 IEEE/ACM International Symposium on Nanoscale Architectures, 70-77, 2011
Smalltalk debug lives in the matrix
L Lagadec, D Picard
International Workshop on Smalltalk Technologies, 11-16, 2010
Towards a framework for designing applications onto hybrid nano/CMOS fabrics
C Dezan, C Teodorov, L Lagadec, M Leuchtenburg, T Wang, ...
Microelectronics journal 40 (4-5), 656-664, 2009
Cardin: An agile environment for edge computing on reconfigurable sensor networks
S Le Xuan, JC Le Lann, L Lagadec, L Fabresse, N Bouraqadi, J Laval
2016 International Conference on Computational Science and Computational …, 2016
A unified design flow to automatically generate on-chip monitors during high-level synthesis of hardware accelerators
MB Hammouda, P Coussy, L Lagadec
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2016
Multilevel simulation of heterogeneous reconfigurable platforms
D Picard, L Lagadec
International Journal of Reconfigurable Computing 2009, 2009
A framework for high-level synthesis of heterogeneous mp-soc
Y Corre, JP Diguet, D Heller, L Lagadec
Proceedings of the great lakes symposium on VLSI, 283-286, 2012
Compiler and System Techniques for soc Distributed Reconfigurable Accelerators
J Cambonie, S Guérin, R Keryell, L Lagadec, B Pottier, O Sentieys, ...
International Workshop on Embedded Computer Systems, 293-302, 2004
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