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Alok Garg
Alok Garg
AMD, University of Rochester
Verified email at amd.com
Title
Cited by
Cited by
Year
An intra-chip free-space optical interconnect
J Xue, A Garg, B Ciftcioglu, J Hu, S Wang, I Savidis, M Jain, R Berman, ...
ACM SIGARCH Computer Architecture News 38 (3), 94-105, 2010
1062010
A performance-correctness explicitly-decoupled architecture
A Garg, MC Huang
2008 41st IEEE/ACM International Symposium on Microarchitecture, 306-317, 2008
552008
A 3-D integrated intrachip free-space optical interconnect for many-core chips
B Ciftcioglu, R Berman, J Zhang, Z Darling, S Wang, J Hu, J Xue, A Garg, ...
IEEE Photonics Technology Letters 23 (3), 164-166, 2010
422010
Injection-locked clocking: A low-power clock distribution scheme for high-performance microprocessors
L Zhang, A Carpenter, B Ciftcioglu, A Garg, M Huang, H Wu
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 16 (9 …, 2008
412008
Software-hardware cooperative memory disambiguation
R Huang, A Garg, M Huang
The Twelfth International Symposium on High-Performance Computer …, 2006
302006
Slackened memory dependence enforcement: Combining opportunistic forwarding with decoupled verification
A Garg, MW Rashid, M Huang
ACM SIGARCH Computer Architecture News 34 (2), 142-154, 2006
282006
Speculative parallelization in decoupled look-ahead
A Garg, R Parihar, MC Huang
2011 International Conference on Parallel Architectures and Compilation …, 2011
192011
Substituting associative load queue with simple hash tables in out-of-order microprocessors
A Garg, F Castro, M Huang, D Chaver, L Pinuel, M Prieto
Proceedings of the 2006 international symposium on Low power electronics and …, 2006
122006
An intra-chip free-space optical interconnect: Extended technical report
J Xue, A Garg, B Ciftcioglu, J Hu, S Wang, I Savidis, M Jain, R Berman, ...
Technical report, Dept. Electrical & Computer Engineering, Univ. of Rochester, 2010
62010
Soft error fault tolerant systems: cs456 survey
A Garg
URL: www. csc. ncsu. edu/faculty/xie/softerrors. html, 2005
62005
Dynamic evaluation and reconfiguration of a data prefetcher
SD Bade, A Garg, J Kalamatianos, P Keltcher, M Evers, C Narasimhaiah
US Patent 9,058,277, 2015
52015
Replacing associative load queues: a timing-centric approach
F Castro, R Noor, A Garg, D Chaver, MC Huang, L Pinuel, M Prieto, ...
IEEE Transactions on Computers 58 (4), 496-511, 2008
52008
Injection-locked clocking: A low-power clock distribution scheme for high-end microprocessors
H Wu, L Zhang, A Carpenter, A Garg, M Huang
Proc. of the 3rd Watson Conference on Interaction between Architecture …, 2006
22006
Implementing software-hardware cooperative memory disambiguation
A Garg, R Huang, M Huang
Technical Report, 2005
22005
Exploring performance-correctness explicitly-decoupled architectures
A Garg
University of Rochester, 2011
12011
Implementation Issues of Slackened Memory Dependence Enforcement
A Garg, M Rashid, M Huang
Technical report, Electrical & Computer Engineering Department, University …, 2006
12006
Array of Pointers Prefetching
CN Keltcher, A Garg, PS Keltcher
US Patent App. 17/704,627, 2023
2023
Load Dependent Branch Prediction
CN Keltcher, A Garg, PS Keltcher
US Patent App. 17/699,855, 2023
2023
Method and apparatus to address row hammer attacks at a host processor
JB Kotra, O Kayiran, J Kalamatianos, A Garg
US Patent App. 17/561,170, 2023
2023
Invariant statistics-based configuration of processor components
A Garg, P Keltcher, M Chhablani, F Eris
US Patent App. 17/217,101, 2022
2022
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