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Yvon Savaria
Yvon Savaria
Professeur in Electrical Engineering, Polytechnique Montreal
Verified email at polymtl.ca
Title
Cited by
Cited by
Year
Reconfigurable pipelined 2-D convolvers for fast digital signal processing
B Bosi, G Bois, Y Savaria
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 7 (3), 299-308, 1999
2131999
A high-efficiency low-voltage CMOS rectifier for harvesting energy in implantable devices
SS Hashemi, M Sawan, Y Savaria
IEEE Transactions on Biomedical Circuits and Systems 6 (4), 326-335, 2012
1732012
GaN integration technology, an ideal candidate for high-temperature applications: A review
A Hassan, Y Savaria, M Sawan
IEEE Access 6, 78790-78802, 2018
1262018
A comparison of automatic word length optimization procedures
MA Cantin, Y Savaria, P Lavoie
2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat …, 2002
1222002
Software detection mechanisms providing full coverage against single bit-flip faults
B Nicolescu, Y Savaria, R Velazco
IEEE Transactions on Nuclear science 51 (6), 3510-3518, 2004
922004
Body electronic implant and artificial vision system thereof
M Sawan, JF Harvey, M Roy, J Coulombe, Y Savaria, C Donfack
US Patent 7,027,874, 2006
902006
Electronics and packaging intended for emerging harsh environment applications: A review
A Hassan, Y Savaria, M Sawan
IEEE transactions on very large scale integration (VLSI) systems 26 (10 …, 2018
802018
Methods, apparatus and system to support large-scale micro-systems including embedded and distributed power supply, thermal regulation, multi-distributedsensors and electrical …
Y Blaquière, Y Savaria, Y Basile-Bellavance, O Valorge, A Lahkssassi, ...
US Patent App. 13/782,868, 2013
782013
An automatic word length determination method
MA Cantin, Y Savaria, D Prodanos, P Lavoie
ISCAS 2001. The 2001 IEEE International Symposium on Circuits and Systems …, 2001
772001
A direct digital period synthesis circuit
DE Calbaza, Y Savaria
IEEE Journal of Solid-State Circuits 37 (8), 1039-1045, 2002
742002
A flexible floating-point format for optimizing data-paths and operators in FPGA based DSPs
J Dido, N Geraudie, L Loiseau, O Payeur, Y Savaria, D Poirier
Proceedings of the 2002 ACM/SIGDA tenth international symposium on Field …, 2002
732002
Automatic test point insertion for pseudo-random testing
Y Savaria, M Youssef, B Kaminska, M Koudil
1991 IEEE International Symposium on Circuits and Systems (ISCAS), 1960-1963, 1991
731991
A novel low-drop CMOS active rectifier for RF-powered devices: Experimental results
S Hashemi, M Sawan, Y Savaria
Microelectronics Journal 40 (11), 1547-1554, 2009
722009
Contact and remote breathing rate monitoring techniques: A review
M Ali, A Elsayed, A Mendez, Y Savaria, M Sawan
IEEE Sensors Journal 21 (13), 14569-14586, 2021
702021
Parallel microprocessor architecture
Y Savaria
US Patent 5,276,893, 1994
661994
Maximizing data transmission rate for implantable devices over a single inductive link: Methodological review
A Trigui, S Hached, AC Ammari, Y Savaria, M Sawan
IEEE reviews in biomedical engineering 12, 72-87, 2018
632018
A high-sensitivity wide input-power-range ultra-low-power RF energy harvester for IoT applications
SM Noghabaei, RL Radin, Y Savaria, M Sawan
IEEE Transactions on Circuits and Systems I: Regular Papers 69 (1), 440-451, 2021
612021
ModelingSegmented-Ladder DACs
D Marche, Y Savaria
IEEE Transactions on Circuits and Systems I: Regular Papers 57 (1), 31-43, 2009
612009
A systolic architecture for fast stack sequential decoders
P Lavoie, D Haccoun, Y Savaria
IEEE Transactions on Communications 42 (234), 324-335, 1994
611994
High voltage charge pump using standard CMOS technology
JF Richard, Y Savaria
The 2nd Annual IEEE Northeast Workshop on Circuits and Systems, 2004. NEWCAS …, 2004
592004
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