Yvon Savaria
Yvon Savaria
Professeur in Electrical Engineering, Polytechnique Montreal
Adresse e-mail validée de polymtl.ca
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Reconfigurable pipelined 2-D convolvers for fast digital signal processing
B Bosi, G Bois, Y Savaria
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 7 (3), 299-308, 1999
1761999
A high-efficiency low-voltage CMOS rectifier for harvesting energy in implantable devices
SS Hashemi, M Sawan, Y Savaria
IEEE Transactions on Biomedical Circuits and Systems 6 (4), 326-335, 2012
1132012
A comparison of automatic word length optimization procedures
MA Cantin, Y Savaria, P Lavoie
2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat …, 2002
1102002
Body electronic implant and artificial vision system thereof
M Sawan, JF Harvey, M Roy, J Coulombe, Y Savaria, C Donfack
US Patent 7,027,874, 2006
852006
Software detection mechanisms providing full coverage against single bit-flip faults
B Nicolescu, Y Savaria, R Velazco
IEEE Transactions on Nuclear science 51 (6), 3510-3518, 2004
852004
A flexible floating-point format for optimizing data-paths and operators in FPGA based DSPs
J Dido, N Geraudie, L Loiseau, O Payeur, Y Savaria, D Poirier
Proceedings of the 2002 ACM/SIGDA tenth international symposium on Field …, 2002
722002
A direct digital period synthesis circuit
DE Calbaza, Y Savaria
IEEE Journal of Solid-State Circuits 37 (8), 1039-1045, 2002
712002
An automatic word length determination method
MA Cantin, Y Savaria, D Prodanos, P Lavoie
ISCAS 2001. The 2001 IEEE International Symposium on Circuits and Systems …, 2001
702001
Automatic test point insertion for pseudo-random testing
Y Savaria, M Youssef, B Kaminska, M Koudil
1991., IEEE International Sympoisum on Circuits and Systems, 1960-1963, 1991
631991
Parallel microprocessor architecture
Y Savaria
US Patent 5,276,893, 1994
611994
A novel low-drop CMOS active rectifier for RF-powered devices: Experimental results
S Hashemi, M Sawan, Y Savaria
Microelectronics Journal 40 (11), 1547-1554, 2009
572009
A systolic architecture for fast stack sequential decoders
P Lavoie, D Haccoun, Y Savaria
IEEE Transactions on Communications 42 (234), 324-335, 1994
551994
Optimal methods of driving interconnections in VLSI circuits
M Nekili, Y Savaria
[Proceedings] 1992 IEEE International Symposium on Circuits and Systems 1, 21-24, 1992
531992
High voltage charge pump using standard CMOS technology
JF Richard, Y Savaria
The 2nd Annual IEEE Northeast Workshop on Circuits and Systems, 2004. NEWCAS …, 2004
522004
Methods, apparatus and system to support large-scale micro-systems including embedded and distributed power supply, thermal regulation, multi-distributedsensors and electrical …
Y Blaquière, Y Savaria, Y Basile-Bellavance, O Valorge, A Lahkssassi, ...
US Patent App. 13/782,868, 2013
502013
Voltage excursion detection apparatus
SMI Adham, Y Savaria, B Antaki, N Xiong
US Patent 6,100,716, 2000
462000
A comparison of self-organizing neural networks for fast clustering of radar pulses
E Granger, Y Savaria, P Lavoie, MA Cantin
Signal Processing 64 (3), 249-269, 1998
441998
Pipelined H-trees for high-speed clocking of large integrated systems in presence of process variations
M Nekili, G Bois, Y Savaria
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 5 (2), 161-174, 1997
441997
Soft-error filtering: A solution to the reliability problem of future VLSI digital circuits
Y Savaria, NC Rumin, JF Hayes, VK Agarwal
Proceedings of the IEEE 74 (5), 669-683, 1986
441986
Optimal design of synchronous circuits using software pipelining techniques
FR Boyer, EM Aboulhamid, Y Savaria, M Boyer
ACM Transactions on Design Automation of Electronic Systems (TODAES) 6 (4 …, 2001
432001
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