| A 0.6-V zero-IF/low-IF receiver with integrated fractional-N synthesizer for 2.4-GHz ISM-band applications A Balankutty, SA Yu, Y Feng, PR Kinget IEEE Journal of Solid-State Circuits 45 (3), 538-553, 2010 | 166 | 2010 |
| Foveros: 3D integration and the use of face-to-face chip stacking for logic devices DB Ingerly, S Amin, L Aryasomayajula, A Balankutty, D Borst, A Chandra, ... 2019 IEEE International Electron Devices Meeting (IEDM), 19.6. 1-19.6. 4, 2019 | 133 | 2019 |
| 3.5 A 16-to-40Gb/s quarter-rate NRZ/PAM4 dual-mode transmitter in 14nm CMOS J Kim, A Balankutty, A Elshazly, YY Huang, H Song, K Yu, F O'Mahony 2015 IEEE International Solid-State Circuits Conference-(ISSCC) Digest of …, 2015 | 112 | 2015 |
| 8.1 Lakefield and Mobility Compute: A 3D Stacked 10nm and 22FFL Hybrid Processor System in 12×12mm2, 1mm Package-on-Package W Gomes, S Khushu, DB Ingerly, PN Stover, NI Chowdhury, F O'Mahony, ... 2020 IEEE International Solid-State Circuits Conference-(ISSCC), 144-146, 2020 | 77 | 2020 |
| A 112 Gb/s PAM-4 56 Gb/s NRZ reconfigurable transmitter with three-tap FFE in 10-nm FinFET J Kim, A Balankutty, RK Dokania, A Elshazly, HS Kim, S Kundu, D Shi, ... IEEE Journal of Solid-State Circuits 54 (1), 29-42, 2018 | 73 | 2018 |
| A 112Gb/s PAM-4 transmitter with 3-Tap FFE in 10nm CMOS J Kim, A Balankutty, R Dokania, A Elshazly, HS Kim, S Kundu, S Weaver, ... 2018 IEEE International Solid-State Circuits Conference-(ISSCC), 102-104, 2018 | 71 | 2018 |
| A 2.4-GHz ISM-band sliding-IF receiver with a 0.5-V supply N Stanic, A Balankutty, PR Kinget, Y Tsividis IEEE Journal of Solid-State Circuits 43 (5), 1138-1145, 2008 | 65 | 2008 |
| 8.1 A 224Gb/s DAC-based PAM-4 transmitter with 8-tap FFE in 10nm CMOS J Kim, S Kundu, A Balankutty, M Beach, BC Kim, S Kim, Y Liu, SK Murthy, ... 2021 IEEE International Solid-State Circuits Conference (ISSCC) 64, 126-128, 2021 | 61 | 2021 |
| A 1.41 pJ/b 224Gb/s PAM-4 SerDes receiver with 31dB loss compensation Y Segal, A Laufer, A Khairi, Y Krupnik, M Cusmai, I Levin, A Gordon, ... 2022 IEEE International Solid-State Circuits Conference (ISSCC) 65, 114-116, 2022 | 50 | 2022 |
| An ultra-low voltage, low-noise, high linearity 900-MHz receiver with digitally calibrated in-band feed-forward interferer cancellation in 65-nm CMOS A Balankutty, PR Kinget IEEE Journal of Solid-State Circuits 46 (10), 2268-2283, 2011 | 50 | 2011 |
| A 224-Gb/s DAC-based PAM-4 quarter-rate transmitter with 8-tap FFE in 10-nm FinFET J Kim, S Kundu, A Balankutty, M Beach, BC Kim, ST Kim, Y Liu, SK Murthy, ... IEEE Journal of Solid-State Circuits 57 (1), 6-20, 2021 | 49 | 2021 |
| A 32 nm SoC with dual core ATOM processor and RF WiFi transceiver H Lakdawala, M Schaecher, CT Fu, R Limaye, J Duster, Y Tan, ... IEEE Journal of Solid-State Circuits 48 (1), 91-103, 2012 | 32 | 2012 |
| Mismatch characterization of ring oscillators A Balankutty, TC Chih, CY Chen, PR Kinget 2007 IEEE Custom Integrated Circuits Conference, 515-518, 2007 | 32 | 2007 |
| Systems and methods for cancelling interferers in a receiver A Balankutty, P Kinget US Patent 8,594,603, 2013 | 30 | 2013 |
| Enabling hybrid bonding on Intel process A Elsherbini, K Jun, R Vreeland, W Brezinski, HK Niazi, Y Shi, Q Yu, ... 2021 IEEE International Electron Devices Meeting (IEDM), 34.3. 1-34.3. 4, 2021 | 29 | 2021 |
| A 2GHz-to-7.5 GHz quadrature clock-generator using digital delay locked loops for multi-standard I/Os in 14nm CMOS A Elshazly, A Balankutty, YY Huang, K Yu, F O'Mahony 2014 Symposium on VLSI Circuits Digest of Technical Papers, 1-2, 2014 | 27 | 2014 |
| A 2.4 GHz WLAN transceiver with fully-integrated highly-linear 1.8 V 28.4 dBm PA, 34dBm T/R switch, 240MS/s DAC, 320MS/s ADC, and DPLL in 32nm SoC CMOS Y Tan, J Duster, CT Fu, E Alpman, A Balankutty, C Lee, A Ravi, ... 2012 Symposium on VLSI Circuits (VLSIC), 76-77, 2012 | 24 | 2012 |
| 32nm x86 OS-compliant PC on-chip with dual-core AtomŽ processor and RF WiFi transceiver H Lakdawala, M Schaecher, C Fu, R Limaye, J Duster, Y Tan, ... 2012 IEEE International Solid-State Circuits Conference, 62-64, 2012 | 23 | 2012 |
| A 1.41-pJ/b 224-Gb/s PAM4 6-bit ADC-based SerDes receiver with hybrid AFE capable of supporting long reach channels A Khairi, Y Krupnik, A Laufer, Y Segal, M Cusmai, I Levin, A Gordon, ... IEEE Journal of Solid-State Circuits 58 (1), 8-18, 2022 | 20 | 2022 |
| A 12-element 60GHz CMOS phased array transmitter on LTCC package with integrated antennas A Balankutty, S Pellerano, T Kamgaing, K Tantwai, Y Palaskas IEEE Asian Solid-State Circuits Conference 2011, 273-276, 2011 | 19 | 2011 |
Frank O'MahonyIntelVerified email at intel.com
