Adrià Armejach
Adrià Armejach
Verified email at bsc.es
TitleCited byYear
EazyHTM: eager-lazy hardware transactional memory
S Tomić, C Perfumo, C Kulkarni, A Armejach, A Cristal, O Unsal, T Harris, ...
Proceedings of the 42nd Annual IEEE/ACM International Symposium on …, 2009
1382009
An empirical evaluation of high-level synthesis languages and tools for database acceleration
O Arcas-Abella, G Ndu, N Sonmez, M Ghasempour, A Armejach, ...
2014 24th International Conference on Field Programmable Logic and …, 2014
472014
MUSA: a multi-level simulation approach for next-generation HPC machines
T Grass, C Allande, A Armejach, A Rico, E Ayguadé, J Labarta, M Valero, ...
Proceedings of the International Conference for High Performance Computing …, 2016
192016
Using a reconfigurable L1 data cache for efficient version management in hardware transactional memory
A Armejach, A Seyedi, R Titos-Gil, I Hur, OS Unsal, M Valero
2011 International Conference on Parallel Architectures and Compilation …, 2011
162011
HARP: Adaptive abort recurrence prediction for hardware transactional memory
A Armejach, A Negi, A Cristal, O Unsal, P Stenstrom, T Harris
20th Annual International Conference on High Performance Computing, 196-205, 2013
142013
Hardware acceleration for query processing: leveraging FPGAs, CPUs, and memory
O Arcas-Abella, A Armejach, T Hayes, GA Malazgirt, O Palomar, B Salami, ...
Computing in Science & Engineering 18 (1), 80, 2015
102015
Circuit design of a dual-versioning L1 data cache for optimistic concurrency
A Seyedi, A Armejach, A Cristal, OS Unsal, I Hur, M Valero
Proceedings of the 21st edition of the great lakes symposium on Great lakes …, 2011
102011
Techniques to improve performance in requester-wins hardware transactional memory
A Armejach, R Titos-Gil, A Negi, OS Unsal, A Cristal
ACM Transactions on Architecture and Code Optimization (TACO) 10 (4), 42, 2013
62013
Tidy cache: Improving data placement in die-stacked DRAM caches
A Armejach, A Cristal, OS Unsal
2015 27th International Symposium on Computer Architecture and High …, 2015
32015
An empirical evaluation of high-level synthesis languages and tools for database acceleration
OA Abella, G Ndu, N Sonmez, M Ghasempour, A Armejach, J Navaridas, ...
The Institute of Electrical and Electronics Engineers, Inc, 2014
32014
Transactional prefetching: narrowing the window of contention in hardware transactional memory
A Negi, A Armejach, A Cristal, OS Unsal, P Stenstrom
Proceedings of the 21st international conference on Parallel architectures …, 2012
32012
Implications of non-volatile memory as primary storage for database management systems
NU Mustafa, A Armejach, O Ozturk, A Cristal, OS Unsal
2016 International Conference on Embedded Computer Systems: Architectures …, 2016
22016
Novel SRAM bias control circuits for a low power L1 data cache
A Seyedi, A Armejach, A Cristal, OS Unsal, M Valero
NORCHIP 2012, 1-6, 2012
22012
Using Arm’s scalable vector extension on stencil codes
A Armejach, H Caminal, JM Cebrian, R Langarita, R González-Alberquilla, ...
The Journal of Supercomputing, 1-24, 2019
12019
Design trade-offs for emerging HPC processors based on mobile market technology
A Armejach, M Casas, M Moretó
The Journal of Supercomputing, 1-24, 2019
12019
Stencil codes on a vector length agnostic architecture
A Armejach, H Caminal, JM Cebrian, R González-Alberquilla, ...
Proceedings of the 27th International Conference on Parallel Architectures …, 2018
12018
Design Space Exploration of Next-Generation HPC Machines
C Gómez, F Martínez, A Armejach, M Moretó, F Mantovani, M Casas
2019
Commit on overflow
S Stipic, A Armejach, OS Unsal, A Cristal Kestelman, M Valero Cortés
2014
Circuit design of a dual-versioning L1 data cache
A Seyedi, A Armejach, A Cristal, OS Unsal, I Hur, M Valero
Integration, the VLSI Journal 45 (3), 237-245, 2012
2012
Transactional Prefetching: Narrowing the Window of Contention in Hardware Transactional Memory
A Armejach, A Negi, A Cristal, OS Unsal, P Stenstrom
7th ACM SIGPLAN Workshop on Transactional Computing, TRANSACT12-Feb, 2012
2012
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Articles 1–20