Zeljko Zilic
Zeljko Zilic
Professor of Electrical and Computer Engineering
Verified email at - Homepage
Cited by
Cited by
Assertion checkers in verification, silicon debug and in-field diagnosis
M Boule, JS Chenard, Z Zilic
8th International Symposium on Quality Electronic Design (ISQED'07), 613-620, 2007
Adding debug enhancements to assertion checkers for hardware emulation and silicon debug
M Boulé, JS Chenard, Z Zilic
2006 International Conference on Computer Design, 294-299, 2006
A comprehensive analysis on wearable acceleration sensors in human activity recognition
M Janidarmian, A Roshan Fekr, K Radecka, Z Zilic
Sensors 17 (3), 529, 2017
A hybrid ring/mesh interconnect for network-on-chip using hierarchical rings for global routing
S Bourduas, Z Zilic
First International Symposium on Networks-on-Chip (NOCS'07), 195-204, 2007
Generating hardware assertion checkers
M Boulé, Z Zilic
Springer, 2008
Using BDDs to Design ULMs for FPGAs
Z Zilic, ZG Vranesic
Proceedings of the 1996 ACM fourth international symposium on Field …, 1996
Automata-based assertion-checker synthesis of PSL properties
M Boule, Z Zilic
ACM Transactions on Design Automation of Electronic Systems (TODAES) 13 (1 …, 2008
FPGA emulation of quantum circuits
AU Khalid, Z Zilic, K Radecka
IEEE International Conference on Computer Design: VLSI in Computers and …, 2004
Incorporating efficient assertion checkers into hardware emulation
M Boulé, Z Zilic
2005 International Conference on Computer Design, 221-228, 2005
Echo cancellation in IP networks
J Radecki, Z Zilic, K Radecka
The 2002 45th Midwest Symposium on Circuits and Systems, 2002. MWSCAS-2002 …, 2002
Architectures of increased availability wireless sensor network nodes
MW Chiang, Z Zilic, K Radecka, JS Chenard
2004 International Conferce on Test, 1232-1241, 2004
The NUMAchine multiprocessor
ZG Vranesic, S Brown, M Stumm, S Caranci, A Grbic, R Grindley, M Gusat, ...
University of Toronto. Computer Systems Research Institute, 1995
Efficient automata-based assertion-checker synthesis of PSL properties
M Boulé, Z Zilic
2006 IEEE International High Level Design Validation and Test Workshop, 69-76, 2006
A blockchain-based eHealthcare system interoperating with WBANs
J Wang, K Han, A Alexandridis, Z Chen, Z Zilic, Y Pang, G Jeon, F Piccialli
Future Generation computer systems 110, 675-685, 2020
Design and evaluation of an intelligent remote tidal volume variability monitoring system in e-health applications
AR Fekr, K Radecka, Z Zilic
IEEE journal of biomedical and health informatics 19 (5), 1532-1548, 2015
A medical cloud-based platform for respiration rate measurement and hierarchical classification of breath disorders
AR Fekr, M Janidarmian, K Radecka, Z Zilic
Sensors 14 (6), 11204-11224, 2014
Automata unit, a tool for designing checker circuitry and a method of manufacturing hardware circuitry incorporating checker circuitry
Z Zilic, M Boulé
US Patent 8,024,691, 2011
Reliability aware NoC router architecture using input channel buffer sharing
MH Neishaburi, Z Zilic
Proceedings of the 19th ACM Great Lakes symposium on VLSI, 511-516, 2009
A laboratory setup and teaching methodology for wireless and mobile embedded systems
JS Chenard, Z Zilic, M Prokic
IEEE Transactions on Education 51 (3), 378-384, 2008
Dynamic clock management for low power applications in FPGAs
I Brynjolfson, Z Zilic
Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No …, 2000
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