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Yipeng Wang
Yipeng Wang
Intel Labs
Verified email at intel.com
Title
Cited by
Cited by
Year
Obfusmem: A low-overhead access obfuscation for trusted memories
A Awad, Y Wang, D Shands, Y Solihin
Proceedings of the 44th Annual International Symposium on Computer …, 2017
1012017
Don’t forget the I/O when allocating your LLC
Y Yuan, M Alian, Y Wang, R Wang, I Kurakin, C Tai, NS Kim
2021 ACM/IEEE 48th Annual International Symposium on Computer Architecture …, 2021
302021
CAF: Core to core communication acceleration framework
Y Wang, R Wang, A Herdrich, J Tsai, Y Solihin
Proceedings of the 2016 International Conference on Parallel Architectures …, 2016
302016
HALO: Accelerating flow classification for scalable packet processing in NFV
Y Yuan, Y Wang, R Wang, J Huang
Proceedings of the 46th International Symposium on Computer Architecture …, 2019
202019
MeToo: Stochastic modeling of memory traffic timing behavior
Y Wang, G Balakrishnan, Y Solihin
2015 International Conference on Parallel Architecture and Compilation (PACT …, 2015
192015
Accelerating open vSwitch with integrated GPU
J Tseng, R Wang, J Tsai, Y Wang, TYC Tai
Proceedings of the Workshop on Kernel-Bypass Networks, 7-12, 2017
172017
Optimizing open vSwitch to support millions of flows
Y Wang, TYC Tai, R Wang, S Gobriel, J Tseng, J Tsai
GLOBECOM 2017-2017 IEEE Global Communications Conference, 1-7, 2017
152017
Flow classification apparatus, methods, and systems
R Wang, TYC Tai, Y Wang, S Gobriel
US Patent 11,088,951, 2021
142021
Systems and methods for modeling memory access behavior and memory traffic timing behavior
Y Solihin, Y Wang, A Awad
US Patent 9,846,627, 2017
122017
Methods and apparatus to facilitate field-programmable gate array support during runtime execution of computer readable instructions
X Guo, S Dutta, H Lee, Y Wang
US Patent 10,445,118, 2019
82019
Technologies for classifying network flows using adaptive virtual routing
Y Wang, R Wang, J Tseng, JS Tsai, TY Tai
US Patent App. 15/999,133, 2019
72019
Processors, methods, and systems to allocate load and store buffers based on instruction type
AJ Herdrich, Y Wang, R Wang, TYC Tai, JS Tsai
US Patent App. 15/089,533, 2017
72017
Hash table design and optimization for software virtual switches
Y Wang, S Gobriel, R Wang, TYC Tai, C Dumitrescu
Proceedings of the 2018 Afternoon Workshop on Kernel Bypassing Networks, 22-28, 2018
62018
Emulating cache organizations on real hardware using performance cloning
Y Wang, Y Solihin
2015 IEEE International Symposium on Performance Analysis of Systems and …, 2015
62015
QEI: Query acceleration can be generic and efficient in the cloud
Y Yuan, Y Wang, R Wang, RBR Chowhury, C Tai, NS Kim
2021 IEEE International Symposium on High-Performance Computer Architecture …, 2021
42021
Technologies for a least recently used cache replacement policy using vector instructions
R Wang, Y Wang, TY Tai, CF Dumitrescu, X Guo
US Patent 10,789,176, 2020
32020
Clone morphing: creating new workload behavior from existing applications
Y Wang, A Awad, Y Solihin
2017 IEEE International Symposium on Performance Analysis of Systems and …, 2017
32017
Accurate cloning of the memory access behavior
A Awad, G Balakrishnan, Y Wang, Y Solihin
IPSJ Transactions on System and LSI Design Methodology 9, 49-60, 2016
32016
Techniques to control an insertion ratio for a cache
Y Wang, R Wang, S Gobriel, TYC Tai
US Patent 10,845,995, 2020
22020
Multi-core communication acceleration using hardware queue device
R Wang, NN Venkatesan, D Bernstein, E Verplanke, SR Van Doren, ...
US Patent 10,445,271, 2019
12019
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