Vivek Joy Kozhikkottu
Vivek Joy Kozhikkottu
Research Scientist, Intel Corp
Verified email at
Cited by
Cited by
SALSA: Systematic logic synthesis of approximate circuits
S Venkataramani, A Sabne, V Kozhikkottu, K Roy, A Raghunathan
DAC Design Automation Conference 2012, 796-801, 2012
TapeCache: A high density, energy efficient cache based on domain wall memory
R Venkatesan, V Kozhikkottu, C Augustine, A Raychowdhury, K Roy, ...
Proceedings of the 2012 ACM/IEEE international symposium on Low power …, 2012
Structures of vertical resistors and FETs as controlled by electrical field penetration and a band-gap voltage reference using vertical FETs operating in accumulation through …
M Chi
US Patent App. 10/268,585, 2004
Cache design with domain wall memory
R Venkatesan, VJ Kozhikkottu, M Sharad, C Augustine, A Raychowdhury, ...
IEEE Transactions on Computers 65 (4), 1010-1024, 2015
VESPA: Variability emulation for System-on-Chip performance analysis
VJ Kozhikkottu, R Venkatesan, A Raghunathan, S Dey
2011 Design, Automation & Test in Europe, 1-6, 2011
Variation aware cache partitioning for multithreaded programs
V Kozhikkottu, A Pan, V Pai, S Dey, A Raghunathan
2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC), 1-6, 2014
Recovery-based design for variation-tolerant SoCs
V Kozhikkottu, S Dey, A Raghunathan
DAC Design Automation Conference 2012, 826-833, 2012
Logic synthesis of approximate circuits
S Venkataramani, VJ Kozhikkottu, A Sabne, K Roy, A Raghunathan
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2019
Energy efficient read/write support for a protected memory
V Kozhikkottu, D Somasekhar, YM Kim, SP Park
US Patent App. 15/089,340, 2017
Optimized memory access bandwidth devices, systems, and methods for processing low spatial locality data
KW Kwon, V Kozhikkottu, SP Park, A More, WP Griffin, R Pawlowski, ...
US Patent App. 15/477,072, 2018
Variation tolerant design of a vector processor for recognition, mining and synthesis
V Kozhikkottu, S Venkataramani, S Dey, A Raghunathan
Proceedings of the 2014 international symposium on Low power electronics and …, 2014
Low latency statistical data bus inversion for energy reduction
V Kozhikkottu, SG Ramasubramanian, KW Kwon, D Somasekhar
US Patent 10,853,300, 2020
Increasing read pending queue capacity to increase memory bandwidth
G Koo, V Kozhikkottu, SG Ramasubramanian, CB Wilkerson
US Patent App. 15/395,615, 2018
Techniques for setting a 2-level auto-close timer to access a memory device
V Kozhikkottu, S Chittor, E Choukse, SG Ramasubramanian
US Patent App. 16/584,612, 2020
Address range based in-band memory error-correcting code protection module with syndrome buffer
AA Radjai, N Aboulenein, SL Geiger, SA Jadhav, BJ Kapadia, ...
US Patent App. 16/504,199, 2019
Memory device with local cache array
JW Lee, V Kozhikkottu, KS Bains, H Alameer
US Patent App. 16/433,663, 2019
Emulation-Based analysis of system-on-chip performance under variations
VJ Kozhikkottu, R Venkatesan, A Raghunathan, S Dey
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 24 (12 …, 2016
Integrated multi-purpose wireless network transceiver
CY Huang
US Patent App. 10/319,461, 2004
System, apparatus and method for application specific address mapping
V Kozhikkottu, E Choukse, SG Ramasubramanian, M Dadual, S Chittor
US Patent 10,936,507, 2021
Minimal Aliasing Single-Error-Correction Codes for DRAM Reliability Improvement
SI Pae, V Kozhikkottu, D Somasekar, W Wu, SG Ramasubramanian, ...
IEEE Access 9, 29862-29869, 2021
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