Bishnu Prasad Das
Bishnu Prasad Das
Associate Professor, IIT, Roorkee
Verified email at iitr.ac.in - Homepage
Title
Cited by
Cited by
Year
Building trusted ICs using split fabrication
K Vaidyanathan, BP Das, E Sumbul, R Liu, L Pileggi
2014 IEEE international symposium on hardware-oriented security and trust …, 2014
1022014
Within-die gate delay variability measurement using reconfigurable ring oscillator
BP Das, B Amrutur, HS Jamadagni, NV Arvind, V Visvanathan
IEEE Transactions on Semiconductor Manufacturing 22 (2), 256-267, 2009
682009
Detecting reliability attacks during split fabrication using test-only BEOL stack
K Vaidyanathan, BP Das, L Pileggi
Proceedings of the 51st Annual Design Automation Conference, 1-6, 2014
402014
Warning prediction sequential for transient error prevention
BP Das, H Onodera
2010 IEEE 25th International Symposium on Defect and Fault Tolerance in VLSI …, 2010
212010
Frequency-Independent Warning Detection Sequential for Dynamic Voltage and Frequency Scaling in ASICs
BP Das, H Onodera
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on 22 (12), 2013
162013
On-chip measurement of rise/fall gate delay using reconfigurable ring oscillator
BP Das, H Onodera
IEEE Transactions on Circuits and Systems II: Express Briefs 61 (3), 183-187, 2014
132014
Gate delay measurement circuit and method of determining a delay of a logic gate
B Amrutur, BP Das
US Patent 8,224,604, 2012
122012
Voltage and temperature scalable gate delay and slew models including intra-gate variations
BP Das, V Janakiraman, B Amrutur, HS Jamadagni, NV Arvind
21st International Conference on VLSI Design (VLSID 2008), 685-691, 2008
112008
Voltage and temperature-aware SSTA using neural network delay model
BP Das, B Amrutur, HS Jamadagni, NV Arvind, V Visvanathan
IEEE transactions on semiconductor manufacturing 24 (4), 533-544, 2011
92011
Voltage and temperature scalable standard cell leakage models based on stacks for statistical leakage characterization
J Viraraghavan, BP Das, B Amrutur
21st International Conference on VLSI Design (VLSID 2008), 667-672, 2008
92008
On-chip threshold voltage variability estimation using reconfigurable ring oscillator
P Jain, BP Das
IEEE Transactions on Semiconductor Manufacturing 32 (2), 226-235, 2019
62019
A metastability immune timing error masking flip-flop for dynamic variation tolerance
G Sannena, BP Das
2016 International Great Lakes Symposium on VLSI (GLSVLSI), 151-156, 2016
62016
Metastability immune and area efficient error masking flip-flop for timing error resilient designs
G Sannena, BP Das
Integration 61, 101-113, 2018
52018
Area-efficient reconfigurable-array-based oscillator for standard cell characterisation
BP Das, H Onodera
IET Circuits, Devices & Systems 6 (6), 429-436, 2012
52012
Low overhead warning flip-flop based on charge sharing for timing slack monitoring
G Sannena, BP Das
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 26 (7 …, 2018
42018
Random Local Delay Variability: On-chip Measurement And Modeling
BP Das
42011
An optimal device sizing for a performance-driven and area-efficient subthreshold cell library for IoT applications
P Sharma, P Jain, BP Das
Microelectronics Journal 92, 104613, 2019
22019
Reducing the impact of local load variation on the DUT in a process detector using a supply controlled ring oscillator
P Jain, BP Das
IEEE Transactions on Semiconductor Manufacturing 32 (4), 605-612, 2019
22019
Testing integrated circuits during split fabrication
L Pileggi, BP Das, K Vaidyanathan
US Patent 10,393,796, 2019
22019
Area and Power-Efficient Timing Error Predictor for Dynamic Voltage and Frequency Scaling Application
G Sannena, BP Das
2016 IEEE International Symposium on Nanoelectronic and Information Systems …, 2016
22016
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