Prashant Nair
Title
Cited by
Cited by
Year
AVATAR: A variable-retention-time (VRT) aware refresh for DRAM systems
MK Qureshi, DH Kim, S Khan, PJ Nair, O Mutlu
2015 45th Annual IEEE/IFIP International Conference on Dependable Systems …, 2015
1902015
ArchShield: Architectural framework for assisting DRAM scaling by tolerating high error rates
PJ Nair, DH Kim, MK Qureshi
ACM SIGARCH Computer Architecture News 41 (3), 72-83, 2013
1792013
Low-cost inter-linked subarrays (LISA): Enabling fast inter-subarray data movement in DRAM
KK Chang, PJ Nair, D Lee, S Ghose, MK Qureshi, O Mutlu
2016 IEEE International Symposium on High Performance Computer Architecture …, 2016
1542016
DEUCE: Write-efficient encryption for non-volatile memories
V Young, PJ Nair, MK Qureshi
ACM SIGARCH Computer Architecture News 43 (1), 33-44, 2015
1222015
A case for refresh pausing in DRAM memory systems
P Nair, CC Chou, MK Qureshi
2013 IEEE 19th International Symposium on High Performance Computer …, 2013
942013
Architectural support for mitigating row hammering in DRAM memories
DH Kim, PJ Nair, MK Qureshi
IEEE Computer Architecture Letters 14 (1), 9-12, 2014
912014
XED: Exposing On-Die Error Detection Information for Strong Memory Reliability
PJ Nair, V Sridharan, MK Qureshi
Computer Architecture (ISCA), 2016 ACM/IEEE 43rd Annual International …, 2016
542016
Reducing read latency of phase change memory via early read and turbo read
PJ Nair, C Chou, B Rajendran, MK Qureshi
2015 IEEE 21st International Symposium on High Performance Computer …, 2015
522015
Citadel: Efficiently protecting stacked memory from TSV and large granularity failures
PJ Nair, DA Roberts, MK Qureshi
ACM Transactions on Architecture and Code Optimization (TACO) 12 (4), 1-24, 2016
492016
Morphable counters: Enabling compact integrity trees for low-overhead secure memories
G Saileshwar, PJ Nair, P Ramrakhyani, W Elsasser, JA Joao, MK Qureshi
2018 51st Annual IEEE/ACM International Symposium on Microarchitecture …, 2018
412018
Synergy: Rethinking secure-memory design for error-correcting memories
G Saileshwar, PJ Nair, P Ramrakhyani, W Elsasser, MK Qureshi
2018 IEEE International Symposium on High Performance Computer Architecture …, 2018
352018
Dice: Compressing dram caches for bandwidth and capacity
V Young, PJ Nair, MK Qureshi
Proceedings of the 44th Annual International Symposium on Computer …, 2017
322017
Reducing refresh power in mobile devices with morphable ECC
C Chou, P Nair, MK Qureshi
2015 45th Annual IEEE/IFIP International Conference on Dependable Systems …, 2015
312015
FaultSim A Fast, Configurable Memory-Reliability Simulator for Conventional and 3D-Stacked Systems
PJ Nair, DA Roberts, MK Qureshi
ACM Transactions on Architecture and Code Optimization (TACO) 12 (4), 1-24, 2015
272015
Refresh pausing in DRAM memory systems
PJ Nair, CC Chou, MK Qureshi
ACM Transactions on Architecture and Code Optimization (TACO) 11 (1), 1-26, 2014
252014
A case for multi-programming quantum computers
P Das, SS Tannu, PJ Nair, M Qureshi
Proceedings of the 52nd Annual IEEE/ACM International Symposium on …, 2019
232019
Taming the instruction bandwidth of quantum computers via hardware-managed error correction
SS Tannu, ZA Myers, PJ Nair, DM Carmean, MK Qureshi
Proceedings of the 50th Annual IEEE/ACM International Symposium on …, 2017
222017
FAULTSIM: A fast, configurable memory-resilience simulator
D Roberts, P Nair
The Memory Forum: In conjunction with ISCA 41, 2014
202014
Attache: Towards ideal memory compression by mitigating metadata bandwidth overheads
S Hong, PJ Nair, B Abali, A Buyuktosunoglu, KH Kim, M Healy
2018 51st Annual IEEE/ACM International Symposium on Microarchitecture …, 2018
162018
Touché: Towards ideal and efficient cache compression by mitigating tag area overheads
S Hong, B Abali, A Buyuktosunoglu, MB Healy, PJ Nair
Proceedings of the 52nd Annual IEEE/ACM International Symposium on …, 2019
82019
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Articles 1–20