| Gate sizing to radiation harden combinational logic Q Zhou, K Mohanram IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2005 | 426 | 2005 |
| Cost-effective approach for reducing soft error failure rate in logic circuits K Mohanram, NA Touba International Test Conference, 2003. Proceedings. ITC 2003. 1, 893-901, 2003 | 367 | 2003 |
| Triple-mode single-transistor graphene amplifier and its applications X Yang, G Liu, AA Balandin, K Mohanram ACS nano 4 (10), 5532-5538, 2010 | 220 | 2010 |
| High performance reliable variable latency carry select addition K Du, P Varman, K Mohanram 2012 design, automation & test in Europe conference & exhibition (DATE …, 2012 | 213 | 2012 |
| Cost-effective radiation hardening technique for combinational logic Q Zhou, K Mohanram IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004 …, 2004 | 153 | 2004 |
| Reliability analysis of logic circuits MR Choudhury, K Mohanram IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2009 | 142 | 2009 |
| Transistor sizing for radiation hardening Q Zhou, K Mohanram 2004 IEEE International Reliability Physics Symposium. Proceedings, 310-315, 2004 | 139 | 2004 |
| Partial error masking to reduce soft error failure rate in logic circuits K Mohanram, NA Touba Proceedings 18th IEEE Symposium on Defect and Fault Tolerance in VLSI …, 2003 | 124 | 2003 |
| TIMBER: Time borrowing and error relaying for online timing error resilience M Choudhury, V Chandra, K Mohanram, R Aitken 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010 …, 2010 | 119 | 2010 |
| An efficient gate library for ambipolar CNTFET logic MH Ben-Jamaa, K Mohanram, G De Micheli IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2011 | 109 | 2011 |
| Dual-Independent-Gate FinFETs for Low Power Logic Circuits M Rostami, K Mohanram IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2011 | 96 | 2011 |
| Approximate logic circuits for low overhead, non-intrusive concurrent error detection MR Choudhury, K Mohanram Proceedings of the conference on Design, automation and test in Europe, 903-908, 2008 | 89 | 2008 |
| Compex++ compression-expansion coding for energy, latency, and lifetime improvements in mlc/tlc nvms PM Palangappa, K Mohanram ACM Transactions on Architecture and Code Optimization (TACO) 14 (1), 1-30, 2017 | 80 | 2017 |
| Novel library of logic gates with ambipolar CNTFETs: Opportunities for multi-level logic synthesis MHB Jamaa, K Mohanram, G De Micheli 2009 Design, Automation & Test in Europe Conference & Exhibition, 622-627, 2009 | 79 | 2009 |
| Parallel domain decomposition for simulation of large-scale power grids K Sun, Q Zhou, K Mohanram, DC Sorensen 2007 IEEE/ACM International Conference on Computer-Aided Design, 54-59, 2007 | 77 | 2007 |
| Accurate and scalable reliability analysis of logic circuits MR Choudhury, K Mohanram 2007 Design, Automation & Test in Europe Conference & Exhibition, 1-6, 2007 | 68 | 2007 |
| SECRET: Smartly encrypted energy efficient non-volatile memories S Swami, J Rakshit, K Mohanram Proceedings of the 53rd Annual Design Automation Conference, 1-6, 2016 | 67 | 2016 |
| Graphene ambipolar multiplier phase detector X Yang, G Liu, M Rostami, AA Balandin, K Mohanram IEEE Electron Device Letters 32 (10), 1328-1330, 2011 | 66 | 2011 |
| Analytical model for TDDB-based performance degradation in combinational logic M Choudhury, V Chandra, K Mohanram, R Aitken 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010 …, 2010 | 66 | 2010 |
| Modeling stochasticity and robustness in gene regulatory networks A Garg, K Mohanram, A Di Cara, G De Micheli, I Xenarios Bioinformatics 25 (12), i101-i109, 2009 | 66 | 2009 |
