Gareth Keane
Gareth Keane
Qualcomm / Qualcomm Ventures
Verified email at wharton.upenn.edu
Title
Cited by
Cited by
Year
The impact of data characteristics and hardware topology on hardware selection for low power DSP
G Keane, J Spanier, R Woods
Proceedings of the 1998 international symposium on Low power electronics and …, 1998
221998
The impact of data characteristics on hardware selection for low-power DSP
G Keane, JR Spanier, R Woods
9th European Signal Processing Conference (EUSIPCO 1998), 1-4, 1998
41998
Low-Power Custom Regular Processor Synthesis Flow
R Woods, G Lightbody, J Spanier, G Keane
Unified low-power design flow for data-dominated multi-media and telecom …, 2000
22000
A Framework for Accurate Power Estimation of Intellectual Property Cores
G Keane, JR Spanier, R Woods
Irish Signal and Systems Conference, 3-10, 1999
21999
VLSI Architectures for High Performance Low Power Signal Processing Applications
G Keane, RF Woods
Irish Digital Signal Processing and Control Conference, 269-276, 1996
21996
Low Power Implementation of a Descrete Cosine Transform IP Core
JR Spanier, G Keane, J Hunter, R Woods
Proc. DATE-2000, 2000
12000
Low power design of signal processing systems using characterization of silicon IP cores
G Keane, JR Spanier, R Woods
Conference Record of the Thirty-Third Asilomar Conference on Signals …, 1999
11999
Algorithms and Architectures for Low Power IC Design
G Keane, R Woods
1
Low-power synthesis flow for regular processor design
R Woods, G Lightbody, A Cassidy, G Keane, J Spanier
IEE Seminar Low Power IC Design, 12/1-12/5, 2001
2001
VLSI architectures for low power applications.
GE Keane
Queen's University of Belfast, 1999
1999
TOWARDS THE DEVELOPMENT OF A POWER-CONSCIOUS HIGH-LEVEL DESIGN FRAMEWORK
G Keane, J Spanier, R Woods
School of Electrical Engineering and Computer Science The Queen's University of Belfast Ashby Building, Stranmillis Road, Belfast BT9 5AH, Northern Ireland
G Keane, JR Spanier, R Woods
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