| Perturb and simplify: multilevel Boolean network optimizer SC Chang, M Marek-Sadowska, KT Cheng IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 1996 | 168 | 1996 |
| Technology mapping for TLU FPGAs based on decomposition of binary decision diagrams SC Chang, M Marek-Sadowdka, TT Hwang IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 1996 | 138 | 1996 |
| Optimization of pattern matching circuits for regular expression on FPGA CH Lin, CT Huang, CP Jiang, SC Chang IEEE Transactions on Very Large Scale Integration (VLSI) Systems 15 (12 …, 2007 | 134 | 2007 |
| Logic synthesis for engineering change CC Lin, KC Chen, M Marek-Sadowska IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 1999 | 133 | 1999 |
| Accelerating pattern matching using a novel parallel algorithm on GPUs CH Lin, CH Liu, LS Chien, SC Chang IEEE Transactions on Computers 62 (10), 1906-1916, 2012 | 102 | 2012 |
| Accelerating string matching using multi-threaded algorithm on GPU CH Lin, SY Tsai, CH Liu, SC Chang, JM Shyu 2010 IEEE Global Telecommunications Conference GLOBECOM 2010, 1-5, 2010 | 96 | 2010 |
| Circuit optimization by rewiring SC Chang, LPPP Van Ginneken, M Marek-Sadowska IEEE Transactions on computers 48 (9), 962-970, 1999 | 86 | 1999 |
| Optimization of regular expression pattern matching circuits on FPGA CH Lin, CT Huang, CP Jiang, SC Chang Design, Automation and Test in Europe, 2006 | 84 | 2006 |
| Timing driven power gating DS Chiou, SH Chen, SC Chang, C Yeh 2006 43rd ACM/IEEE Design Automation Conference, 121-124, 2006 | 69 | 2006 |
| Layout driven logic synthesis for FPGAs SC Chang, KT Cheng, NS Woo, M Marek-Sadowska Design Automation Conference 4 (g5), o1, 1994 | 67 | 1994 |
| Postlayout logic restructuring using alternative wires SC Chang, KT Cheng, NS Woo, M Marek-Sadowska IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 1997 | 66 | 1997 |
| Fast Boolean optimization by rewiring SC Chang, LPPP van Ginneken, M Marek-Sadowska Proceedings of International Conference on Computer Aided Design, 262-269, 1996 | 66 | 1996 |
| Performance optimization using variable-latency design style YS Su, DC Wang, SC Chang, M Marek-Sadowska IEEE transactions on very large scale integration (VLSI) systems 19 (10 …, 2010 | 61 | 2010 |
| Monas: Multi-objective neural architecture search using reinforcement learning CH Hsu, SH Chang, JH Liang, HP Chou, CH Liu, SC Chang, JY Pan, ... arXiv preprint arXiv:1806.10332, 2018 | 57 | 2018 |
| A fuzzy-matching model with grid reduction for lithography hotspot detection WY Wen, JC Li, SY Lin, JY Chen, SC Chang IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2014 | 49 | 2014 |
| Technology mapping via transformations of function graphs SC Chang, M Marek-Sadowska Proceedings 1992 IEEE International Conference on Computer Design: VLSI in …, 1992 | 46 | 1992 |
| A novel fuzzy matching model for lithography hotspot detection SY Lin, JY Chen, JC Li, W Wen, SC Chang 2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC), 1-6, 2013 | 45 | 2013 |
| Minimizing ROBDD size of incompletely specified multiple output functions SC Chang, D kin Cheng, M Marek-Sadowska European Design and Test Conference, 1994 | 42 | 1994 |
| Thermal-aware on-line task allocation for 3D multi-core processor throughput optimization CL Lung, YL Ho, DM Kwai, SC Chang 2011 Design, Automation & Test in Europe, 1-6, 2011 | 41 | 2011 |
| Fine-grained sleep transistor sizing algorithm for leakage power minimization DS Chiou, DC Juan, YT Chen, SC Chang Proceedings of the 44th annual Design Automation Conference, 81-86, 2007 | 36 | 2007 |
Da-Cheng JuanGoogle Research, National Tsing Hua University, Carnegie Mellon UniversityVerified email at dacheng.info
