Booster: Reactive Core Acceleration for Mitigating the Effects of Process Variation and Application Imbalance in Low-Voltage Chips TN Miller, X Pan, R Thomas, N Sedaghati, R Teodorescu 2012 IEEE 18th International Symposium on High Performance Computer …, 2012 | 103 | 2012 |
VRSync: Characterizing and Eliminating Synchronization-Induced Voltage Emergencies in Many-Core Processors TN Miller, R Thomas, X Pan, R Teodorescu ACM SIGARCH Computer Architecture News 40 (3), 249-260, 2012 | 77 | 2012 |
NVSleep: Using Non-Volatile Memory to Enable Fast Sleep/Wakeup of Idle Cores X Pan, R Teodorescu 2014 IEEE 32nd International Conference on Computer Design (ICCD), 400-407, 2014 | 22 | 2014 |
NVCool: When Non-Volatile Caches Meet Cold Boot Attacks X Pan, A Bacha, S Rudolph, L Zhou, Y Zhang, R Teodorescu 2018 IEEE 36th International Conference on Computer Design (ICCD), 439-448, 2018 | 13 | 2018 |
Using STT-RAM to Enable Energy-Efficient Near-Threshold Chip Multiprocessors X Pan, R Teodorescu Proceedings of the 23rd International Conference on Parallel Architectures …, 2014 | 6 | 2014 |
Respin: Rethinking Near-Threshold Multiprocessor Design with Non-Volatile Memory X Pan, A Bacha, R Teodorescu Parallel and Distributed Processing Symposium (IPDPS), 2017 IEEE …, 2017 | 4 | 2017 |
Designing Future Low-Power and Secure Processors with Non-Volatile Memory X Pan The Ohio State University, 2017 | 1 | 2017 |