Virtual simulation of distributed IP-based designs M Dalpasso, A Bogliolo, L Benini
Proceedings of the 36th annual ACM/IEEE Design Automation Conference, 50-55, 1999
56 1999 Specification and validation of disstributed IP-based designs with JavaCAD M Dalpasso, A Bogliolo, L Benini
Proceedings of the conference on Design, automation and test in Europe, 132-es, 1999
51 1999 Fault simulation of parametric bridging faults in CMOS IC's M Dalpasso, M Favalli, P Olivo, B Ricco
IEEE transactions on computer-aided design of integrated circuits and …, 1993
29 1993 Parametric Bridging Fault Characterieation for the Fault Simulation of Library-Based ICs M Dalpasso, M Favalli, P Olivo, B Riccò
Proceedings International Test Conference 1992, 486-486, 1992
24 1992 Hardware/software IP protection M Dalpasso, A Bogliolo, L Benini
Proceedings of the 37th Annual Design Automation Conference, 593-596, 2000
23 2000 Bridging fault modeling and simulation for deep submicron CMOS ICs M Favalli, M Dalpasso
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2002
20 2002 Analysis of dynamic effects of resistive bridging faults in CMOS and BiCMOS digital ICs M Favalli, M Dalpasso, P Olivo, B Ricco
Proceedings of IEEE International Test Conference-(ITC), 865-874, 1993
18 1993 Analysis of steady state detection of resistive bridging faults in BiCMOS digital ICs M Favalli, M Dalpasso, P Olivo, B Ricco
Proceedings International Test Conference 1992, 466-466, 1992
16 1992 Modeling of broken connections faults in CMOS ICs M Favalli, M Dalpasso, P Olivo, B Ricco
Proceedings of European Design and Test Conference EDAC-ETC-EUROASIC, 159-164, 1994
14 1994 Self-learning signature analysis for non-volatile memory testing P Olivo, M Dalpasso
Proceedings International Test Conference 1996. Test and Design Validity …, 1996
12 1996 High quality test vectors for bridging faults in the presence of IC's parameters variations M Favalli, M Dalpasso
22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI …, 2007
10 2007 Modeling and simulation of broken connections in CMOS IC's M Favalli, M Dalpasso, P Olivo
IEEE transactions on computer-aided design of integrated circuits and …, 1996
10 1996 Switch-Level fault simulation by critical-path tracing M Dalpasso, M Favalli, P Olivo, B Ricco
IEEE European Test Conference 1991, 181-190, 1991
9 1991 Boolean and pseudo-boolean test generation for feedback bridging faults M Favalli, M Dalpasso
IEEE Transactions on Computers 65 (3), 706-715, 2015
8 2015 Algorithmic strategies for a fast exploration of the TSP -OPT neighborhood G Lancia, M Dalpasso
Journal of Heuristics, 1-36, 2023
7 2023 Virtual fault simulation of distributed IP-based designs M Dalpasso, A Bogliolo, L Benini, M Favalli
Proceedings of the conference on Design, automation and test in Europe, 99-105, 2000
7 2000 Correlation between IDDQ Testing Quality and Sensor Accuracy M Dalpasso, M Favalli, P Olivo
European Design and Test Conference, 1995. ED&TC 1995, Proceedings, 568-572, 1995
7 * 1995 Realistic testability estimates for CMOS ICs M Dalpasso, M Favalli, P Olivo, JP Teixeira
Electronics Letters 30 (19), 1593-1595, 1994
7 1994 Analysis of resistive bridging fault detection in BiCMOS digital ICs M Favalli, M Dalpasso, P Olivo, B Ricco
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 1 (3), 342-355, 1993
6 1993 Applications of boolean satisfiability to verification and testing of switch-level circuits M Favalli, M Dalpasso
Journal of Electronic Testing 30, 41-55, 2014
5 2014