| Hardmask designs for dry etching FeRAM capacitor stacks T Moise, SR Gilbert, SR Summerfelt, G Xing, L Colombo US Patent 6,534,809, 2003 | 344 | 2003 |
| A monolithic 4-bit 2-Gsps resonant tunneling analog-to-digital converter TPE Broekaert, B Brar, JPA van der Wagt, AC Seabaugh, FJ Morris, ... IEEE Journal of Solid-State Circuits 33 (9), 1342-1349, 1998 | 261 | 1998 |
| Integrated circuit and method TS Moise, G Xing, M Visokay, JF Gaynor, SR Gilbert, F Celii, ... US Patent 6,211,035, 2001 | 259 | 2001 |
| Quantitative simulation of a resonant tunneling diode RC Bowen, G Klimeck, RK Lake, WR Frensley, T Moise Journal of applied physics 81 (7), 3207-3213, 1997 | 204 | 1997 |
| Quantum device simulation with a generalized tunneling formula G Klimeck, R Lake, RC Bowen, WR Frensley, TS Moise Applied physics letters 67 (17), 2539-2541, 1995 | 180 | 1995 |
| A 64-Mb embedded FRAM utilizing a 130-nm 5LM Cu/FSG logic process HP McAdams, R Acklin, T Blake, XH Du, J Eliason, J Fong, WF Kraus, ... IEEE Journal of Solid-State Circuits 39 (4), 667-677, 2004 | 124 | 2004 |
| Integrated circuit and method TS Moise, G Xing, M Visokay, JF Gaynor, SR Gilbert, F Celii, ... US Patent 6,444,542, 2002 | 115 | 2002 |
| Reliability properties of low-voltage ferroelectric capacitors and memory arrays JA Rodriguez, K Remack, K Boku, KR Udayakumar, S Aggarwal, ... IEEE Transactions on Device and Materials Reliability 4 (3), 436-449, 2004 | 101 | 2004 |
| Sputtering process for the conformal deposition of a metallization or insulating layer PC Van Buskirk, MW Russell, DJ Vestyck, SR Summerfelt, TS Moise US Patent 6,100,200, 2000 | 92 | 2000 |
| Fabricating an embedded ferroelectric memory cell T Moise, S Summerfelt, E Zielinski, S Johnson US Patent 6,734,477, 2004 | 87 | 2004 |
| Method of fabricating a ferroelectric memory cell SR Summerfelt, TS Moise, G Xing, L Colombo, T Sakoda, SR Gilbert, ... US Patent 6,548,343, 2003 | 84 | 2003 |
| Method of patterning a FeRAM capacitor with a sidewall during bottom electrode etch SR Summerfelt, G Xing, L Colombo, S Aggarwal, TS Moise IV US Patent 6,635,498, 2003 | 82 | 2003 |
| Ferroelectric capacitor stack etch cleaning methods SR Summerfelt, LH Hall, KR Udayakumar, TS Moise IV US Patent 7,220,600, 2007 | 77 | 2007 |
| Demonstration of a 4 Mb, high density ferroelectric memory embedded within a 130 nm, 5 LM Cu/FSG logic process TS Moise, SR Summerfelt, H McAdams, S Aggarwal, KR Udayakumar, ... Digest. International Electron Devices Meeting,, 535-538, 2002 | 68 | 2002 |
| SOC CMOS technology for personal internet products D Buss, BL Evans, J Bellay, W Krenik, B Haroun, D Leipold, K Maggio, ... IEEE Transactions on Electron Devices 50 (3), 546-556, 2003 | 67 | 2003 |
| Magnitude, origin, and evolution of piezoelectric optical nonlinearities in strained [111] B InGaAs/GaAs quantum wells AN Cartwright, DS McCallum, TF Boggess, AL Smirl, TS Moise, LJ Guido, ... Journal of applied physics 73 (11), 7767-7774, 1993 | 66 | 1993 |
| Hydrogen barrier for protecting ferroelectric capacitors in a semiconductor device and methods for fabricating the same KR Udayakumar, MG Albrecht, TS Moise IV, SR Summerfelt, S Aggarwal, ... US Patent 6,984,857, 2006 | 64 | 2006 |
| Optically switched resonant tunneling diodes TS Moise, YC Kao, LD Garrett, JC Campbell Applied physics letters 66 (9), 1104-1106, 1995 | 61 | 1995 |
| Reliability of Ferroelectric Random Access memory embedded within 130nm CMOS J Rodriguez, K Remack, J Gertas, L Wang, C Zhou, K Boku, ... 2010 IEEE International Reliability Physics Symposium, 750-758, 2010 | 60 | 2010 |
| Method of forming an FeRAM having a multi-layer hard mask and patterning thereof SR Summerfelt, S Aggarwal, L Colombo, TS Moise IV, JS Martin US Patent 6,828,161, 2004 | 57 | 2004 |
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