| A 65 nm 2-billion transistor quad-core Itanium processor B Stackhouse, S Bhimji, C Bostak, D Bradley, B Cherkauer, J Desai, ... IEEE Journal of Solid-State Circuits 44 (1), 18-31, 2008 | 277 | 2008 |
| The xeon® processor e5-2600 v3: A 22 nm 18-core product family B Bowhill, B Stackhouse, N Nassif, Z Yang, A Raghavan, O Mendoza, ... IEEE Journal of Solid-State Circuits 51 (1), 92-104, 2015 | 84 | 2015 |
| The 16 kB single-cycle read access cache on a next-generation 64 b Itanium microprocessor D Bradley, P Mahoney, B Stackhouse 2002 IEEE International Solid-State Circuits Conference. Digest of Technical …, 2002 | 30 | 2002 |
| In-band margin probing on an operational interconnect DS Froelich, DD Sharma, F Spagna, PE Fornberg, DE Bradley US Patent 10,671,476, 2020 | 19 | 2020 |
| A power and area efficient 2.5-16 Gbps gen4 PCIe PHY in 10nm FinFET CMOS S Li, F Spagna, J Chen, X Wang, L Tong, S Gowder, W Jia, R Nicholson, ... 2018 IEEE Asian Solid-State Circuits Conference (A-SSCC), 5-8, 2018 | 10 | 2018 |
| In-band margin probing on an operational interconnect DS Froelich, DD Sharma, F Spagna, PE Fornberg, DE Bradley US Patent 11,157,350, 2021 | 4 | 2021 |
| 486042 Method to determine write robustness of custom random access memory circuits B Stackhouse, DE Bradley, CJ Little RESEARCH DISCLOSURE, 1306-1306, 2004 | | 2004 |
| SPECIAL ISSUE ON THE 2008 IEEE INTERNATIONAL SOLID-STATE CIRCUITS CONFERENCE (ISSCC) YO Otaguro, S Parampalli, M Steigerwald, S Gundala, R Pyapali, ... | | |
| ISSCC 2002/SESSION 6/SRAM AND NON-VOLATILE MEMORIES/6.6 D Bradley, BS Patrick Mahoney | | |
