Marie Garcia Bardon
Marie Garcia Bardon
Η διεύθυνση ηλεκτρονικού ταχυδρομείου έχει επαληθευτεί στον τομέα
Παρατίθεται από
Παρατίθεται από
Pseudo-two-dimensional model for double-gate tunnel FETs considering the junctions depletion regions
MG Bardon, HP Neves, R Puers, C Van Hoof
IEEE Transactions on electron Devices 57 (4), 827-834, 2010
Vertical GAAFETs for the ultimate CMOS scaling
D Yakimets, G Eneman, P Schuddinck, TH Bao, MG Bardon, P Raghavan, ...
IEEE Transactions on Electron Devices 62 (5), 1433-1439, 2015
Device exploration of nanosheet transistors for sub-7-nm technology node
D Jang, D Yakimets, G Eneman, P Schuddinck, MG Bardon, P Raghavan, ...
IEEE Transactions on Electron Devices 64 (6), 2707-2713, 2017
Self-heating on bulk FinFET from 14nm down to 7nm node
D Jang, E Bury, R Ritzenthaler, MG Bardon, T Chiarella, K Miyaguchi, ...
2015 IEEE International Electron Devices Meeting (IEDM), 11.6. 1-11.6. 4, 2015
Understanding energy efficiency benefits of carbon nanotube field-effect transistors for digital VLSI
G Hills, MG Bardon, G Doornbos, D Yakimets, P Schuddinck, R Baert, ...
IEEE Transactions on Nanotechnology 17 (6), 1259-1269, 2018
Power aware FinFET and lateral nanosheet FET targeting for 3nm CMOS technology
D Yakimets, MG Bardon, D Jang, P Schuddinck, Y Sherazi, P Weckx, ...
2017 IEEE International Electron Devices Meeting (IEDM), 20.4. 1-20.4. 4, 2017
Extreme scaling enabled by 5 tracks cells: Holistic design-device co-optimization for FinFETs and lateral nanowires
MG Bardon, Y Sherazi, P Schuddinck, D Jang, D Yakimets, P Debacker, ...
2016 IEEE International Electron Devices Meeting (IEDM), 28.2. 1-28.2. 4, 2016
High-mobility 0.85nm-EOT Si0.45Ge0.55-pFETs: Delivering high performance at scaled VDD
J Mitard, L Witters, MG Bardon, P Christie, J Franco, A Mercha, ...
2010 International Electron Devices Meeting, 10.6. 1-10.6. 4, 2010
Holisitic device exploration for 7nm node
P Raghavan, MG Bardon, D Jang, P Schuddinck, D Yakimets, J Ryckaert, ...
2015 IEEE Custom Integrated Circuits Conference (CICC), 1-5, 2015
Vertical device architecture for 5nm and beyond: Device & circuit implications
AVY Thean, D Yakimets, TH Bao, P Schuddinck, S Sakhare, MG Bardon, ...
2015 Symposium on VLSI Technology (VLSI Technology), T26-T27, 2015
The impact of sequential-3D integration on semiconductor scaling roadmap
A Mallik, A Vandooren, L Witters, A Walke, J Franco, Y Sherazi, P Weckx, ...
2017 IEEE International Electron Devices Meeting (IEDM), 32.1. 1-31.1. 4, 2017
Design technology co-optimization for N10
J Ryckaert, P Raghavan, R Baert, MG Bardon, M Dusa, A Mallik, ...
Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 1-8, 2014
Dimensioning for power and performance under 10nm: the limits of FinFETs scaling
M Garcia Bardon, P Schuddinck, P Raghavan, D Jang, D Yakimets, ...
ICICDT, 2015
Layout-induced stress effects in 14nm & 10nm FinFETs and their impact on performance
MG Bardon, V Moroz, G Eneman, P Schuddinck, M Dehan, D Yakimets, ...
2013 Symposium on VLSI Technology, T114-T115, 2013
Low track height standard cell design in iN7 using scaling boosters
SMY Sherazi, C Jha, D Rodopoulos, P Debacker, B Chava, L Matti, ...
Design-Process-Technology Co-optimization for Manufacturability XI 10148 …, 2017
Architectural strategies in standard-cell design for the 7 nm and beyond technology node
SMY Sherazi, B Chava, P Debacker, MG Bardon, P Schuddinck, F Firouzi, ...
Journal of Micro/Nanolithography, MEMS, and MOEMS 15 (1), 013507, 2016
Scaling of BTI reliability in presence of time-zero variability
H Kükner, P Weckx, J Franco, M Toledano-Luque, M Cho, B Kaczer, ...
2014 IEEE International Reliability Physics Symposium, CA. 5.1-CA. 5.7, 2014
Limitations on lateral nanowire scaling beyond 7-nm node
UK Das, MG Bardon, D Jang, G Eneman, P Schuddinck, D Yakimets, ...
IEEE Electron Device Letters 38 (1), 9-11, 2016
Lateral versus vertical gate-all-around FETs for beyond 7nm technologies
D Yakimets, TH Bao, MG Bardon, M Dehan, N Collaert, A Mercha, Z Tokei, ...
72nd Device Research Conference, 133-134, 2014
Stacked nanosheet fork architecture for SRAM design and device co-optimization toward 3nm
P Weckx, J Ryckaert, V Putcha, A De Keersgieter, J Boemmels, ...
2017 IEEE International Electron Devices Meeting (IEDM), 20.5. 1-20.5. 4, 2017
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