Saša Tomić
Saša Tomić
Verified email at zurich.ibm.com
TitleCited byYear
EazyHTM: eager-lazy hardware transactional memory
S Tomić, C Perfumo, C Kulkarni, A Armejach, A Cristal, O Unsal, T Harris, ...
Proceedings of the 42nd Annual IEEE/ACM International Symposium oná…, 2009
1422009
Background threshold voltage shifting using base and delta threshold voltage shift values in non-volatile memory
CJ Camp, TJ Fisher, AD Fry, N Ioannou, I Koltsidas, N Papandreou, ...
US Patent App. 10/222,997, 2019
352019
Background threshold voltage shifting using base and delta threshold voltage shift values in flash memory
CJ Camp, TJ Fisher, AD Fry, N Ioannou, I Koltsidas, N Papandreou, ...
US Patent 9,251,909, 2016
252016
The velox transactional memory stack
P Felber, E Riviere, WM Moreira, D Harmanci, P Marlier, S Diestelhorst, ...
Micro, IEEE 30 (5), 76-87, 2010
24*2010
Wear leveling of a memory array
TJ Fisher, AD Fry, N Ioannou, I Koltsidas, J Ma, RA Pletka, LT Simmons, ...
US Patent 10,082,962, 2018
232018
Threshold voltage shifting at a lower bit error rate by intelligently performing dummy configuration reads
N Ioannou, N Papandreou, RA Pletka, S Tomic
US Patent 10,170,195, 2019
182019
A Comprehensive Study of Conflict Resolution Policies in Hardware Transactional Memory
E Akpinar, S Tomić, A Cristal, O Unsal, V Mateo
TRANSACT, 2011
182011
Reducing write amplification in solid-state drives by separating allocation of relocate writes from user writes
CJ Camp, TJ Fisher, AD Fry, N Ioannou, I Koltsidas, R Pletka, S Tomic
US Patent 9,632,927, 2017
152017
Dynamic filtering: multi-purpose architecture support for language runtime systems
T Harris, S Tomic, A Cristal, O Unsal
ACM Sigplan Notices 45 (3), 39-52, 2010
152010
Wear leveling of a memory array
TJ Fisher, AD Fry, N Ioannou, I Koltsidas, J Ma, RA Pletka, LT Simmons, ...
US Patent 9,857,986, 2018
132018
Detecting error count deviations for non-volatile memory blocks for advanced non-volatile memory block management
CJ Camp, TJ Fisher, AD Fry, N Ioannou, R Pletka, S Tomic
US Patent 9,563,373, 2017
122017
Cooperative data deduplication in a solid state storage array
TJ Fisher, N Ioannou, I Koltsidas, RA Pletka, S Tomic
US Patent App. 14/576,247, 2016
122016
Health-binning: Maximizing the performance and the endurance of consumer-level NAND flash
RA Pletka, S Tomić
Proceedings of the 9th ACM International on Systems and Storage Conference, 4, 2016
122016
Method and device for managing a memory
N Ioannou, I Koltsidas, RA Pletka, S Tomic, TD Weigold
US Patent 9,760,309, 2017
102017
Storage array management employing a merged background management process
CJ Camp, TJ Fisher, AD Fry, N Ioannou, RA Pletka, LT Simmons, S Tomic
US Patent 10,365,859, 2019
92019
Non-volatile memory system having an increased effective number of supported heat levels
CJ Camp, TJ Fisher, AD Fry, N Ioannou, I Koltsidas, R Pletka, S Tomic
US Patent 10,078,582, 2018
92018
Non-volatile memory data storage with low read amplification
N Ioannou, I Koltsidas, T Mittelholzer, T Parnell, R Pletka, C Pozidis, ...
US Patent 9,710,199, 2017
92017
Endurance enhancement scheme using memory re-evaluation
CJ Camp, TJ Fisher, AD Fry, N Ioannou, I Koltsidas, R Pletka, S Tomic
US Patent 10,339,048, 2019
82019
Adaptive health grading for a non-volatile memory
S Tomic, RA Pletka
US Patent 10,254,981, 2019
72019
Non-volatile memory controller cache architecture with support for separation of data streams
CJ Camp, TJ Fisher, AD Fry, N Ioannou, I Koltsidas, R Pletka, S Tomic, ...
US Patent 9,779,021, 2017
72017
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